LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 159
![no-image](/images/no-image-200.jpg)
LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
- Current page: 159 of 284
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General-Purpose Timers
159
Reset
Reset
Type
Type
GPTM TimerB (GPTMTBR)
Offset 0x04C
31:16
RO
RO
31
15
0
1
15:0
Bit
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge
Count mode. When in this mode, this register contains the time at which the last edge event took
place.
RO
RO
30
14
0
1
reserved
Name
TBRL
RO
RO
29
13
0
1
RO
RO
28
12
0
1
Type
RO
RO
RO
RO
27
11
0
1
RO
RO
26
10
0
1
0xFFFF
Reset
0
RO
RO
25
0
9
1
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM TimerB
A read returns the current value of the TimerB Count Register,
except in Input Edge Count mode, when it returns the
timestamp from the last edge event.
RO
RO
24
0
8
1
reserved
TBRL
RO
RO
23
0
7
1
RO
RO
22
0
6
1
RO
RO
21
0
5
1
RO
RO
20
0
4
1
RO
RO
19
0
3
1
RO
RO
18
0
2
1
March 22, 2006
RO
RO
17
0
1
1
RO
RO
16
0
0
1
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