LM3S101-CRN20-XNPP ETC1 [List of Unclassifed Manufacturers], LM3S101-CRN20-XNPP Datasheet - Page 220
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LM3S101-CRN20-XNPP
Manufacturer Part Number
LM3S101-CRN20-XNPP
Description
Microcontroller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-CRN20-XNPP.pdf
(284 pages)
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12.2.4
12.2.4.1
March 22, 2006
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
SSI can only generate a single interrupt request to the controller at any given time. You can mask
each of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt
Mask (SSIIM) register (see page 235). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt
Status (SSIMIS) registers (see page 236 and page 237, respectively).
Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and National Semiconductor MICROWIRE frame formats, the serial frame
(SSIFss) pin is active Low, and is asserted (pulled down) during the entire transmission of the
frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame
format, both the SSI and the off-chip slave device drive their output data on the rising edge of
SSIClk, and latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the National Semiconductor
MICROWIRE format uses a special master-slave messaging technique, which operates at half-
duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip
slave. During this transmit, no incoming data is received by the SSI. After the message has been
sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit
control message has been sent, responds with the requested data. The returned data can be 4 to
16 bits in length, making the total frame length anywhere from 13 to 25 bits.
Texas Instruments Synchronous Serial Frame Format
Figure 12-2 shows the Texas Instruments synchronous serial frame format for a single transmitted
frame.
Figure 12-2.
Texas Instruments synchronous serial
Freescale SPI
National Semiconductor MICROWIRE
SSITx/SSIRx
SSIClk
SSIFss
TI Synchronous Serial Frame Format (Single Transfer)
MSB
Preliminary
4 to 16 bits
LSB
LM3S101 Data Sheet
220
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