LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 17
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LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
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Inter-Integrated Circuit (I
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CAN ............................................................................................................................................... 401
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Register 4:
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Register 8:
June 04, 2007
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 343
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 345
SSI Data (SSIDR), offset 0x008 ...................................................................................... 347
SSI Status (SSISR), offset 0x00C ................................................................................... 348
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 349
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 350
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 351
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 352
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 353
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 354
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 355
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 356
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 357
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 358
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 359
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 360
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 361
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 362
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 363
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 364
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 365
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CAN Control (CANCTL), offset 0x000 ............................................................................. 415
CAN Status (CANSTS), offset 0x004 ............................................................................... 417
CAN Error Counter (CANERR), offset 0x008 ................................................................... 420
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 421
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 423
CAN Test (CANTST), offset 0x014 .................................................................................. 424
CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 426
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 427
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 380
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 381
C Master Data (I2CMDR), offset 0x008 ......................................................................... 385
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 386
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 387
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 388
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 389
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 390
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 391
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 393
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 394
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 396
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 397
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 398
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 399
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 400
2
C) Interface ........................................................................................ 366
Preliminary
LM3S2965 Microcontroller
17
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