LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 340
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LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
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Synchronous Serial Interface (SSI)
14.3
340
Figure 14-12 on page 340 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1.
2.
3.
4.
5.
As an example, assume the SSI must be configured to operate with the following parameters:
SSIRx
Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
Select whether the SSI is a master or slave:
a.
b.
c.
Configure the clock prescale divisor by writing the SSICPSR register.
Write the SSICR0 register with the following configuration:
■
■
■
■
Enable the SSI by setting the SSE bit in the SSICR1 register.
Serial clock rate (SCR)
Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
The data size (DSS)
For master operations, set the SSICR1 register to 0x00000000.
For slave mode (output enabled), set the SSICR1 register to 0x00000004.
For slave mode (output disabled), set the SSICR1 register to 0x0000000C.
t
Hold
Preliminary
=t
t
Setup
SSIClk
=(2*t
SSIClk
)
First RX data to be
sampled by SSI slave
June 04, 2007
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