LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 26
LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
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Architectural Overview
26
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UART
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ADC
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Analog Comparators
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I
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2
C
Three fully programmable 16C550-type UARTs with IrDA support
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
Programmable baud-rate generator with fractional divider
Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
FIFO trigger levels of 1/8, ¼, ½, ¾, and 7/8
Standard asynchronous communication bits for start, stop, and parity
False-start-bit detection
Line-break generation and detection
Single- and differential-input configurations
Four 10-bit channels (inputs) when used as single-ended inputs
Sample rate of one million samples/second
Flexible, configurable analog-to-digital conversion
Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
On-chip temperature sensor
Three independent integrated analog comparators
Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
Compare external pin input to external pin input or to internal programmable voltage reference
Two I
Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
Interrupt generation
2
C modules
Preliminary
June 04, 2007
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