LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 429

• Manufacturer Part Number: LM3S2965-IQN25-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

June 04, 2007
Bit/Field
5
4
3
2
TxRqst/NewDat
ClrIntPnd
Control
Name
Arb
Type
R/W
R/W
R/W
R/W
Reset
0x0
0x0
0x0
0x0
Preliminary
Description
Access Arbitration Bits
When WRNRD=1 (writes):
0: Arbitration bits unchanged.
1: Transfer ID + Dir + Xtd + MsgVal to message object.
When WRNRD=0 (reads):
0: Arbitration bits unchanged.
1: Transfer ID + Dir + Xtd + MsgVal to Message Buffer Register.
Access Control Bits
When WRNRD=1 (writes):
0: Control bits unchanged.
1: Transfer control bits to message object.
When WRNRD=0 (reads):
0: Control bits unchanged.
1: Transfer control bits to Message Buffer Register.
Clear Interrupt Pending Bit
Note:
0: IntPnd bit in CANIFnMCTL register remains unchanged.
1: Clear IntPnd bit in the CANIFnMCTL register in the message object.
When WRNRD=1 (writes):
Access Transmission Request Bit
0: TxRqst bit unchanged.
1: Set TxRqst bit
Note:
When WRNRD=0 (reads):
Access New Data Bit
0: NewDat bit unchanged.
1: Clear NewDat bit in the message object.
Note:
This bit is not used when in write (WRNRD=1).
If a transmission is requested by programming this TxRqst
bit, the parallel TxRqst in the CANIFnMCTL register is
ignored.
A read access to a message object can be combined with the
reset of the control bits IntPdn and NewDat. The values of
these bits that are transferred to the CANIFnMCTL register
always reflect the status before resetting these bits.
LM3S2965 Microcontroller
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