LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 368

• Manufacturer Part Number: LM3S2965-IQN25-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Inter-Integrated Circuit (I
15.2.1.3 Data Validity
15.2.1.4 Acknowledge
368
Figure 15-4. Complete Data Transfer with a 7-Bit Address
The first seven bits of the first byte make up the slave address (see Figure 15-5 on page 368). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 15-5. R/S Bit in First Byte
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is low (see Figure 15-6 on page 368).
Figure 15-6. Data Validity During Bit Transfer on the I
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 368.
When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
MSB
SDA
SCL
SDA
SCL
Slave address
2
C) Interface
MSB
1
Data line
Slave address
stable
2
allowed
Chan ge
of data
LSB
7
LSB
R/S
R/S
8
Preliminary
ACK
9
MSB
1
2
2
C Bus
Data
7
LSB
8
ACK
9
June 04, 2007