SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 42

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Multi-Port Memory Controller
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12.1
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Multi-Port Memory Controller
Overview
The DRAM interface is controlled by the on-chip Multi-Port Memory Controller.
Its main features are:
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Table 9.
Table 10.
16 (2 MB x 8 bits)
16 (1 MB x 16 bits)
64 (8 MB x 8 bits)
64 (4 MB x 16 bits)
64 (2 MB x 32 bits)
128 (16 MB x 8 bits)
128 (8 MB x 16 bits)
128 (4 MB x 32 bits)
256 (32 MB x 8 bits)
256 (16 MB x 16 bits)
256 (8 MB x 32 bits)
512 (64 MB x 8 bits)
512 (32 MB x 16 bits)
0
1
2
3
PORT
Supports for SDRAM up to 32 bit wide
Supports for DDR up to 16 bit wide
Maximum clock frequency 133 MHz
8 AHB port connections
4 chip selects
Total addressable memory: 256 MB
Maximum memory bank size: 64 MB
Read and Write buffers to reduce latency
Programmable timings
SIZE [MB]
Multi-Port Memory Controller AHB port assignment
Supported memory cuts
SIZE [bit]
32
32
32
-
BANK NUMBER
PRIORITY
2
2
4
4
4
4
4
4
4
4
4
4
4
Max
Bus Matrix
Reserved
eASIC™
USB 2.0 Device
ROW LENGTH
12
12
13
11
11
12
12
11
12
13
13
13
13
MASTER
COLUMN LENGTH
SPEAR-09-H022
10
10
11
10
9
8
9
8
8
9
8
9
8