SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 9

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPEAR-09-H022
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Product Overview
SPEAr Head200 is a powerful System on Chip based on 110nm HCMOS and consists of 2
main parts: an ARM based architecture and an embedded customizable logic block.
The high performance ARM architecture frees the user from the task of developing a
complete RISC system.
The customizable logic block allows user to design custom logic and special functions.
SPEAr Head200 is optimized for embedded applications and thanks to its high performance
can be used for a wide range of different purposes.
Main blocks description:
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Bus System supports two masters: the ARM926EJ-S and the Customizable Logic
block, connected to AHB Bus. All others blocks are slaves.
CPU: ARM926EJ-S running at 266 MHz.
It has:
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Main Bus System: a complete AMBA Bus 2.0 subsystem connects different masters
and slaves.
The subsystem includes:
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Clock and Reset System: fully programmable block with:
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Interrupt Controller: the Interrupt Controller has 32 interrupt sources which are
prioritized and vectorized.
On-chip memory: 4 independent static RAM cuts, 4 KB each, are available.
They can be used on AHB Bus or directly by the custom logic.
Dynamic Memory Controller: it is a Multi-Port Memory Controller which is able to
connect directly to memory sizes from 16 to 512 Mbits; the data size can be 8 or 16 bits
for both DDR and SDRAM, also 32 bits for SDRAM. The external data bus can be
maximum 32 bit wide at maximum clock frequency of 133 MHz and have up to 4 chip
selects; the accessible memory is 256 MB.
Internally it handles 7 ports supporting the following masters: AHB Bus, Bus Matrix, 2
USB 2.0 Hosts, USB 2.0 Device, Ethernet MAC, eASIC™ MacroCell.
MMU
32 KB of instruction CACHE
16 KB of data CACHE
8 KB of instruction TCM (Tightly Coupled Memory)
8 KB of data TCM
AMBA Bus interface
Coprocessor interface
JTAG
ETM9 (Embedded Trace Macro-cell) for debug; large size version.
AHB Bus, for high performance devices
APB Bus, for low power / lower speed devices connectivity
Bus Matrix, for improving connection between the peripherals
Separated set-up between clocks of AHB Bus and APB Bus peripherals
E.M.I. reduction mode, replacing all traditional drop methods for Electro-Magnetic
Interference
Debug mode, compliant with ARM debug status
Product Overview
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