SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 46

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPI memories
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SPI memories
Overview
SPEAr Head200 supports the SPI memory devices Flash and EEPROM.
SPI controller, also called Serial Memory Interface (SMI), provides an AHB slave interface to
SPI memories and allows CPU to use them as data storage or code execution.
Main features are
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The compatible SPI memories are:
The I/O interfaces accessible from off-chip are listed here:
Figure 11. SPI Interfaces
Table 13.
SMIDATAIN
SMIDATAOUT
SMICLK
SMINCS
SPI master type
Up to 20 MHz clock speed in Standard Read mode and 50 MHz in Fast Read mode
4 chips select
Up to 16 MBytes address space per bank
Selectable 3 Byte addressing for Flash and 2 Byte addressing for EEPROM
Programmable clock prescaler
External memory boot mode capability
32, 16 or 8 bit AHB interface
Interrupt request on write complete or software transfer complete
–
–
–
–
–
SMIDATAIN
Signal
STMicroelectronics M25Pxxx, M45Pxxx
STMicroelectronics M95xxx except M95040, M95020 and M95010
ATMEL AT25Fxx
YMC Y25Fxx
SST SST25LFxx
SPI signal interfaces description
Direction
Output
Output
Output
Input
SPI
Size [bit]
1
1
1
4
Memory input
Memory output
Memory clock
Bankchip selects (active low)
Description
SPEAR-09-H022
SMINCS
SMICLK
SMIDATAOUT