SPEAR-09-H022_06 STMICROELECTRONICS [STMicroelectronics], SPEAR-09-H022_06 Datasheet - Page 44

• Manufacturer Part Number: SPEAR-09-H022_06
• Description: SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Multi-Port Memory Controller
12.2
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MPMC DELAY LINES
As shown in
The CLOCKOUT delay line is used to tuner the clock driven from MPMC to external DRAM
to match setup / hold constraints on external memory. This Delay Lines is used in the "clock
delay methodology" suitable for SDRAM memory.
The AHB Bus Delay Lines delays the DRAM command signal (ADDR, CAS, RAS, ...) to
capture easily read data from DRAM; this technique is called "command delay".
The DQSINL and DQSINH Delay Lines delay respectively the DQS0 (least 8 bit data strobe)
and DQS1 (highest 8 bit of data strobe) signals coming from DDR.
Only the least 7 bits of these registers are significant because the Delay Lines programming
parameter can vary from 0 to 127.
Figure 10. MPMC DLL
AHB Bus clock
Figure
HCLK
DLL
10, there are 4 DLLsp.
HCLK_DLY
COMMAND
MPMC
DRIVER
DRAM
SDR
DDR
ADDR, CAS, RAS, WE, ..
DATA_IN
DQS
DATA_OUT
CLOCKOUT
DLL
DQSINL
DQSINU
DLL
SPEAR-09-H022
DDR