OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet - Page 33

• Manufacturer Part Number: OX16PCI954-TQC60-A
• Description: Integrated Quad UART and PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

Note 10:
To read or write to any of the Indexed Controlled Registers use the following procedure:
Writing to ICR registers:
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).
Write the desired offset to SPR (address 111b).
Write the desired value to ICR (address 101b).
Reading from ICR registers:
Ensure that the last value written to LCR was not 0xBF (see above).
Write 0x00 offset to SPR to select ACR.
Set bit 6 of ACR (ICR read enable) by writing x1xxxxxxb to address 101b. Ensure that other bits in ACR are not changed.
(Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!)
Write the desired offset to SPR (address 111b).
Read the desired value from ICR (address 101b).
Write 0x00 offset to SPR to select ACR.
Clear bit 6 of ACR bye writing x0xxxxxxb to ICR, thus enabling access to standard registers again.
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
Register
Name
MDM
NMR
ACR
CPR
CKS
REV
CSR
GDS
TCR
FCH
RFC
TTL
RTL
FCL
ID1
ID2
ID3
The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the Indexed Control Registers via ICR.
Offset values not listed in the table are reserved for future use and must not be used.
Offset
SPR
0x0C
0x0D
0X0F
0X10
0x0A
0x0B
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
Unused
Unused
Unused
Unused
FCR[7]
Enable
Status
Bit 7
Addit-
Tx 1x
Mode
ional
0
0
Unused
Table 17: Indexed Control Register Set
Indexed Control Register Set
Tx CLK
FCR[6]
Enable
Select
Bit 6
Read
ICR
0
0
5 Bit “integer” part of
Unused
clock prescaler
SChar 4
wakeup
BDOUT
on DTR
Enable
disable
FCR[5]
Trigger
Bit 5
9
Level
950
SIN
th
reset the UART (Except the CKS register)
0
Automatic Flow Control Lower Trigger Level (0-127)
Automatic Flow Control Higher Trigger level (1-127)
Bit
Writing 0x00 to this register will
Hardwired revision byte (0x01)
Transmitter Interrupt Trigger Level (0-127)
Hardwired ID byte 1 (0xC9)
Hardwired ID byte 1 (0x16)
Hardwired ID byte 1 (0x50)
Receiver Interrupt Trigger Level (1-127)
SChar 3
Wakeup
Modem
Disable
DTR 1x
Tx CLK
FCR[4]
Bit 4
DTR definition and
9
th
0
Bit
control
SChar 2
Wakeup
disable
FCR[3]
Bit 3
9
Rx 1x
Mode
th
DCD
0
Bit
SChar 1
RI edge
Control
Enable
Trailing
disable
FCR[2]
Bit 2
4 Bit N-times clock
9
selection bits [3:0]
Auto
DSR
Flow
th
0
0
Bit
3 Bit “fractional” part of
clock prescaler
9
Wakeup
Disable
disable
FCR[1]
th
Bit 1
-bit Int.
En.
Tx
DSR
0
Clock Sel[1:0]
OX16PCI954
Receiver
Wakeup
Disable
Enable
disable
FCR[0]
Page 33
Bit 0
status
Good
9 Bit
data
Rx
CTS