OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet - Page 31

• Manufacturer Part Number: OX16PCI954-TQC60-A
• Description: Integrated Quad UART and PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

7.2
Each UART is accessed through an 8-byte block of I/O space (or through memory space). Since there are more than 8 registers,
the mapping is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1.
2.
3.
4.
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
Register
650 mode
750 mode
950 mode
9-bit data
9-bit data
650/950
550/750
550/750
650/950
Name
MCR
Normal
Normal
LSR
MSR
RHR
IER
THR
FCR
LCR
SPR
Mode
Mode
Mode
Mode
mode
mode
ISR
LCR[7]=1 enables the divider latch registers DLL and DLM.
LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
ACR[7]=1 enables access to the 950 specific registers.
ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 33.
DLM
DLL
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
Register description tables
1,2
3,5
3
3,4
4
1
3
3
1
3
Address
000
000
001
010
010
011
100
101
110
111
000
001
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
interrupt
prescale
access
Divisor
Bit 7
mask
Baud
Error
CTS
latch
Data
DCD
Table 14: Standard 550 Compatible Registers
RHR Trigger
RHR Trigger
enabled
Unused
Unused
FIFOs
Level
Level
Tx Empty
interrupt
Bit 6
mask
break
mode
RTS
IrDA
Tx
RI
Unused
XON-Any
Alternate
Divisor latch bits [15:8] (Most significant byte)
Special
Control
Divisor latch bits [7:0] (Least significant byte)
Detect
CTS &
Empty
Bit 5
mode
Force
parity
Char.
sleep
FIFO
(Enhanced mode)
Size
RTS
Flow
THR
DSR
Interrupt priority
Indexed control register offset value bits
THR Trigger
Temporary data storage register and
Level
Data to be transmitted
Unused
Internal
Unused
Enable
Bit 4
Sleep
Break
mode
Odd /
parity
Loop
Back
even
CTS
Rx
Data received
interrupt
Framing
Modem
Enable
Trigger
enable
Bit 3
Parity
mask
Delta
Error
DCD
Tx
Unused
Interrupt priority
(All modes)
interrupt
Number
RI edge
Rx Stat
data bit
Trailing
of stop
Bit 2
Flush
Parity
9
mask
Error
THR
bits
th
Rx
interrupt
Overrun
Bit 1
THRE
mask
Flush
Delta
Error
RHR
DSR
RTS
Data length
OX16PCI954
interrupt
Interrupt
pending
RxRDY
RxRDY
Enable
data bit
Page 31
Bit 0
mask
Delta
9
FIFO
DTR
CTS
th
Tx