OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet - Page 50

• Manufacturer Part Number: OX16PCI954-TQC60-A
• Description: Integrated Quad UART and PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

The above facility produces an interrupt for recognizing any
‘address’ characters. Alternatively, the user can configure
the UART to compare the receiver data stream with up to
four programmable 9-bit characters and assert a level 5
interrupt after detecting a match. The interrupt occurs when
the character is transferred to the FIFO (See below).
NMR[0]: 9-bit mode enable
logic 0
logic 1
NMR[1]: Enable interrupt when 9
logic 0
logic 1
Special Character Detection
While the UART is in both 9-bit mode and Enhanced mode,
setting IER[5] will enable detection of up to four ‘address’
characters. The least significant eight bits of these four
programmable characters are stored in special characters
1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode)
registers and the 9
programmed in NMR[5] to NMR[2] respectively.
NMR[2]: Bit 9 of Special Character 1
NMR[3]: Bit 9 of Special Character 2
NMR[4]: Bit 9 of Special Character 3
NMR[5]: Bit 9 of Special Character 4
NMR[7:6]: Reserved
Bits 6 and 7 of NMR are always cleared and reserved for
future use.
7.11.10 Modem Disable Mask ‘MDM’
The MDM register is located at offset 0x0E of the ICR
This register is cleared after a hardware reset to maintain
compatibility with 16C550. It allows the user to mask
interrupts, sleep operation and power management events
due to individual modem lines or the serial input line.
MDM[0]: Disable delta CTS
logic 0
logic 1
MDM[1]: Disable delta DSR
logic 0
Data Sheet Revision 1.3
OXFORD SEMICONDUCTOR LTD.
9-bit mode is disabled.
9-bit mode is enabled.
Receiver interrupt for detection of an ‘address’
character (i.e. 9
Receiver interrupt for detection of an ‘address’
character (i.e. 9
1 interrupt is asserted.
Delta CTS is enabled. It can generate a level 4
interrupt when enabled by IER[3]. In power-
state D2, delta CTS can assert the PME# line.
Delta CTS can wake up the UART when it is
asleep under auto-sleep operation.
interrupt, assert a PME# or wake up the UART.
Delta DSR is enabled. It can generate a level 4
interrupt when enabled by IER[3]. In power-
state D2, delta DSR can assert the PME# line.
Delta CTS is disabled. In can not generate an
th
bit of these characters are
th
th
bit set) is disabled.
bit set) is enabled and a level
th
bit is set
logic 1
MDM[2]: Disable Trailing edge RI
logic 0
logic 1
MDM[3]: Disable delta DCD
logic 0
logic 1
MDM[4]: Reserved
This bit must be set to ‘0’
MDM[5]: Disable SIN wake up
logic 0
logic 1
MDM[7:6]: Reserved
7.11.11 Readable FCR ‘RFC’
The RFC register is located at offset 0x0F of the ICR
This read-only register returns the current state of the FCR
register (Note that FCR is write-only). This register is
included for diagnostic purposes.
7.11.12 Good-data status register ‘GDS’
The GDS register is located at offset 0x10 of the ICR
For the definition of Good-data status refer to section 6.4.7.
GDS[0]: Good Data Status
GDS[7:1]: Reserved
Delta DSR can wake up the UART when it is
asleep under auto-sleep operation.
interrupt, assert a PME# or wake up the UART.
Trailing edge RI is enabled. It can generate a
level 4 interrupt when enabled by IER[3]. In
power-state D2, trailing edge RI can assert the
PME# line. Trailing edge RI can wake up the
UART when it is asleep under auto-sleep
operation.
generate an interrupt, assert a PME# or wake
up the UART.
Delta DCD is enabled. It can generate a level 4
interrupt when enabled by IER[3]. In power-
state D2, delta DCD can assert the PME# line.
Delta DCD can wake up the UART when it is
asleep under auto-sleep operation.
interrupt, assert a PME# or wake up the UART.
When the device is in power-down state D2, a
change in the state of the serial input line (i.e.
start bit) can assert the PME# line
When the device is in power-down state D2, a
change in the state of the serial input line
cannot assert the PME# line.
Delta DSR is disabled. In can not generate an
Trailing edge RI is disabled. In can not
Delta DCD is disabled. In can not generate an
OX16PCI954
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