OX16PCI954-TQC60-A OXFORD [Oxford Semiconductor], OX16PCI954-TQC60-A Datasheet - Page 21

• Manufacturer Part Number: OX16PCI954-TQC60-A
• Description: Integrated Quad UART and PCI interface
• Manufacturer: OXFORD [Oxford Semiconductor]

Note 1:
Data Sheet Revision 1.3
Bits
15:12
19:16
23:20
27:24
31:28
OXFORD SEMICONDUCTOR LTD.
Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. These parameters apply to both 8-bit and 32-bit Local Bus
configurations. See notes in the following page.
Description
Write Chip-select De-assertion (Intel-type interface). Defines the number
of clock cycles after the reference cycle when the LBCS[3:0]# pins are
de-asserted (high) during a write operation to the Local Bus.
Read-not-Write De-assertion during write cycles (Motorola-type
interface). Defines the number of clock cycles after the reference cycle
when the LBRDWR# pin is de-asserted (high) during a write to the Local
Bus.
Read Control Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBRD# pin is asserted
(low) during a read from the Local Bus.
Read Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are asserted (low) during a read from the Local Bus.
Read Control De-assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBRD# pin is de-
asserted (high) during a read from the Local Bus.
Read Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are de-asserted (high) during a read from the Local Bus.
Write Control Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBWR# pin is asserted
(low) during a write to the Local Bus.
Write Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are asserted (low) during a write to the Local Bus.
Write Control De-assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBWR# pin is de-
asserted (high) during a write to the Local Bus.
Write Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are de-asserted (high) during a write cycle to the Local Bus.
1
1
1
1
1
1
1
1
1
1
EEPROM
Read/Write
W
W
W
W
W
PCI
RW
RW
RW
RW
RW
OX16PCI954
parallel port)
parallel port)
parallel port)
(1h for
(2h for
(1h for
Reset
2h
0h
3h
0h
2h
Page 21