DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 11

• Manufacturer Part Number: DSM2150F5V
• Description: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

Main Flash Memory
The 4M bit (512 KByte) Main Flash memory is di-
vided into eight equally-sized 64 KByte sectors
that are individually selectable through the De-
code PLD. Each Flash memory sector can be lo-
cated at any address as defined by the user with
PSDsoft Express. DSP code and data are easily
placed in flash memory using PSDsoft Express,
the software development tool.
Secondary Flash Memory
The 256Kbit (32 KByte) Secondary Flash memory
is divided into eight equally-sized 8 KByte sectors
that are individually selectable through the De-
code PLD. Each Flash memory sector can be lo-
cated at any address as defined by the user with
PSDsoft Express. DSP code and data can also be
placed Secondary Flash memory using the PSD-
soft Express development tool.
Secondary flash memory is good for storing data
because of its smaller sectors. Software EEPROM
emulation techniques can be used for small data
sets that change frequently on a byte-by-byte ba-
sis.
Secondary flash may also be used to store custom
start-up code for applications that do not “boot” us-
ing DMA, but instead start executing code from ex-
ternal memory upon reset (bypass internal DSP
boot ROM). Storing code here can keep the entire
Main Flash free of initialization code for clean soft-
ware partitioning. If only one or more 8 KByte sec-
tors are needed for start-up code, the remaining
sectors of Secondary Flash may be used for data
storage.
In-Application-Programming (IAP) may be imple-
mented using Secondary Flash. For example,
code to implement IAP over a USB channel may
be stored here. The DSP executes code from Sec-
ondary Flash array while erasing and writing new
code to the Main Flash array as it is received over
the USB channel. Any communication channel
that the DSP supports can be used for IAP.
Secondary Flash may also be used as an exten-
sion to Main Flash memory producing a total of
544 KBytes.
Miscellaneous: Main and Secondary Flash memo-
ries are totally independent, allowing concurrent
operation. The DSP can read from one memory
while erasing or programming the other. The DSP
can erase Flash memories by individual sectors or
the entire Flash memory array may be erased at
one time. Each sector in either Flash memory ar-
ray may be individually write protected, blocking
any WRITEs from the DSP (good for boot and
start-up code protection). The Flash memories au-
tomatically go to standby between DSP READ or
WRITE accesses to conserve power. Maximum
access times include sector decoding time. Maxi-
mum erase cycles is 100K and data retention is 15
years minimum. Flash memory, as well as the en-
tire DSM device may be programmed with the
JTAG ISP interface with no DSP involvement.
Programmable Logic (PLDs)
The DSM family contains two PLDS that may op-
tionally run in Turbo or Non-Turbo Mode. PLDs op-
erate faster (less propagation delay) while in
Turbo Mode but consume more power than Non-
Turbo Mode. Non-Turbo Mode allows the PLDs to
automatically go to standby when no inputs are
change to conserve power. The Turbo Mode set-
ting is controlled at runtime by DSP software.
Decode PLD (DPLD). This is programmable log-
ic used to select one of the eight individual Main
Flash memory segments, one of four individual
Secondary Flash memory segments, or the group
of control registers within the DSM device. The
DPLD can also drive external chip select signals
on Port C pins. DPLD input signals include: DSP
address and control signals, Page Register out-
puts, DSM Port Pins, CPLD logic feedback.
Complex PLD (CPLD). This programmable logic
is used to create both combinatorial and sequen-
tial general purpose logic. The CPLD contains 16
Output Macrocells (OMCs) and 24 Input Macro-
cells (IMCs). PSD Macrocell registers are unique
in that they have direct connection to the DSP data
bus allowing them to be loaded and read directly
by the DSP at runtime. This direct access is good
for making small peripheral devices (shiftier,
counters, state machines, etc.) that are accessed
directly by the DSP with little overhead. DPLD in-
puts include DSP address and control signals,
Page Register outputs, DSM Port Pins, and CPLD
feedback.
OMCs: The general structure of the CPLD is simi-
lar in nature to a 22V10 PLD device with the famil-
iar sum-of-products (AND-OR) construct. True
and compliment versions of 73 input signals are
available to a large AND array. AND array outputs
feed into a multiple product-term OR gate within
each OMC (up to 10 product-terms for each
OMC). Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flip-
flop within in each OMC to realize sequential logic.
OMCs can be used as a buried nodes with feed-
back to the AND array or OMC output can be rout-
ed to pins on Port A or Port B.
IMCs: Inputs from pins on Ports A, B or C are rout-
ed to IMCs for conditioning (clocking or latching)
as they enter the chip, which is good for sampling
and debouncing inputs. Alternatively, IMCs can
pass Port input signals directly to PLD inputs with-
out clocking or latching. The DSP may read the
IMCs at any time.
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