DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 26

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DSM2150F5V

Manufacturer Part Number
DSM2150F5V
Description
DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
Manufacturer
STMicroelectronics
Datasheet

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DSM2150F5V
Decode PLD (DPLD)
The DPLD, shown in Figure 7, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
Figure 7. DPLD Logic Array
26/73
MCELLA.FB [ 7:0] (Feedback)
MCELLB.FB [ 7:0] (Feedback )
PG0-PG7
I/O PORTS (PORT A, B,C)
A[15:0]
PD[3:0]
CNTRL[2:0] (Read/Write Control Signals)
RESET
RD_BSY
8 Main Flash memory Sector Select (FS0-
FS7) signals with three product terms each
4 Secondary Flash memory Sector Select
(CSBOOT0-CSBOOT3) signals with three
product terms each
(INPUTS)
(24)
(16)
(8)
(8)
(8)
(4)
(1)
(1)
(3)
1 internal csiop select for DSM device control
and status registers (csiop is the base address
of the block of 256 byte locations)
1 JTAG Select signal (enables JTAG
operations on Port E when multiplexing JTAG
signals with general I/O signals)
8 external chip select output signals for Port C
pins, each with one product term.
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
CSIOP
JTAGSEL
ECS0
ECS1
ECS2
ECS3
ECS4
ECS5
ECS6
ECS7
FS0
FS1
FS7
FS2
FS3
FS5
FS6
FS4
CSBOOT0
CSBOOT1
CSBOOT2
CSBOOT3
I/O Decoder
Select
JTAG ISP
External Chip Selects
to PORT C
8 Flash Main
Memory
Sector Selects
4 Secondary
Flash Memory
Sector Selects
AI05775

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