DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 70

• Manufacturer Part Number: DSM2150F5V
• Description: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

DSM2150F5V
Table 41. Output Macrocells A Register
Note: Bit Definitions:
Table 42. Output Macrocells B Register
Note: Bit Definitions:
Table 43. Mask Macrocells A Register
Note: Bit Definitions:
Table 44. Mask Macrocells B Register
Note: Bit Definitions:
Table 45. Flash Memory Protection Register
Note: Bit Definitions (Read only register):
Table 46. Flash Boot Protection Register
Note: Bit Definitions:
Table 47. JTAG Enable Register
Note: Bit Definitions:
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Bit 7
Mcella 7
Bit 7
Mcellb 7
Bit 7
Mcella 7
Bit 7
Mcellb 7
Bit 7
Sec7_Prot
Bit 7
Security_Bit
Bit 7
not used
Write Register: Load MCellA7-MCellA0 with 0 or 1.
Read Register: Read MCellA7-MCellA0 output status.
Write Register: Load MCellB7-MCellB0 with 0 or 1.
Read Register: Read MCellB7-MCellB0 output status.
McellA<i>_Prot 0 = Allow MCellA<i> flip-flop to be loaded by MCU (default).
McellA<i>_Prot 1 = Prevent MCellA<i> flip-flop from being loaded by DSP.
McellB<i>_Prot 0 = Allow MCellB<i> flip-flop to be loaded by MCU (default).
McellB<i>_Prot 1 = Prevent MCellB<i> flip-flop from being loaded by DSP.
Sec<i>_Prot 1 = Primary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Primary Flash memory Sector <i> is not write protected.
Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
JTAGEnable 1 = JTAG Port is enabled.
JTAGEnable 0 = JTAG Port is disabled.
Bit 6
Mcella 6
Bit 6
Mcellb 6
Bit 6
Mcella 6
Bit 6
Mcellb 6
Bit 6
Sec6_Prot
Bit 6
not used
Bit 6
not used
Bit 5
Mcella 5
Bit 5
Mcellb 5
Bit 5
Mcella 5
Bit 5
Mcellb 5
Bit 5
Sec5_Prot
Bit 5
not used
Bit 5
not used
Bit 4
Mcella 4
Bit 4
Mcellb 4
Bit 4
Mcella 4
Bit 4
Mcellb 4
Bit 4
Sec4_Prot
Bit 4
not used
Bit 4
not used
Bit 3
not used
Bit 3
Mcella 3
Bit 3
Mcellb 3
Bit 3
Mcella 3
Bit 3
Mcellb 3
Bit 3
Sec3_Prot
Bit 3
Sec3_Prot
Bit 2
not used
Bit 2
Mcella 2
Bit 2
Mcellb 2
Bit 2
Mcella 2
Bit 2
Mcellb 2
Bit 2
Sec2_Prot
Bit 2
Sec2_Prot
Bit 1
not used
Bit 1
Mcella 1
Bit 1
Mcellb 1
Bit 1
Mcella 1
Bit 1
Mcellb 1
Bit 1
Sec1_Prot
Bit 1
Sec1_Prot
Bit 0
JTAG Enable
Bit 0
Mcella 0
Bit 0
Mcellb 0
Bit 0
Mcella 0
Bit 0
Mcellb 0
Bit 0
Sec0_Prot
Bit 0
Sec0_Prot