DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 17

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DSM2150F5V

Manufacturer Part Number
DSM2150F5V
Description
DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
Manufacturer
STMicroelectronics
Datasheet

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Table 6. Instruction Sequences for 16-bit Operation (Notes 1,2,3,4,15)
Note: 1. All values are in hexadecimal, X = “Don’t care”
Read Memory
Contents
Read Flash
Identifier (Main
Flash only)
Read Sector
Protect Status
Program a Flash
word
Flash Bulk Erase
Flash Sector
Erase
Suspend Sector
Erase
Resume Sector
Erase
Reset Flash
Unlock Bypass
Unlock Bypass
Program
Unlock Bypass
Reset
Instruction
Sequence
2. A desired internal Flash memory sector select signal (FS0 - FS7 or CSBOOT0 - CSBOOT3) must be active for each WRITE or
3. Only address Bits A11-A0 are used during Flash memory instruction sequence decoding bus cycles. The individual sector select
4. For WRITE operations, addresses are latched on the falling edge of Write Strobe (WR, CNTL0), Data is latched on the rising edge
5. No Unlock or Instruction cycles are required when the device is in the Read Array Mode. Operation is like reading a ROM device.
6. The Reset Flash instruction is required to return to the normal Read Array Mode if the Error Flag Bit (DQ5) goes High, or after read-
10
11
12
14
READ cycle. Only one of these sector select signals will be active at any given time depending on the address presented by the
DSP and the memory mapping defined in PSDsoft Express. FS0 - FS7 and CSBOOT0-CSBOOT3 are active high logic internally.
signal (FS0 - FS7 or CSBOOT0-CSBOOT3) which is active during the instruction sequences determines the complete address.
of Write Strobe (WR, CNTL0)
ing the Flash Identifier or after reading the Sector Protection Status.
13
5
6,7
6
6,7,8
9
Read word
from even
addr
Write XXAAh
to XXAAAh
Write XXAAh
to XXAAAh
Write XXAAh
to XXAAAh
Write XXAAh
to XXAAAh
Write XXAAh
to XXAAAh
Write XXB0h
to even addr in
FS0-7 or
CSBOOT0-3
Write XX30h
to even addr in
FS0-7 or
CSBOOT0-3
Write XXF0h
to even addr in
FS0-7 or
CSBOOT0-3
Write XXAAh
to XXAAAh
Write XXA0h
to even addr in
FS0-7 or
CSBOOT0-3
Write XX90h
to even addr in
FS0-7 or
CSBOOT0-3
Cycle 1
Write XX55h
to XX554h
Write XX55h
to XX554h
Write XX55h
to XX554h
Write XX55h
to XX554h
Write XX55h
to XX554h
Write XX55h
to XX554h
Write word
to even addr
Write XX00h
to even addr
in FS0-7 or
CSBOOT0-3
Cycle 2
Write XX90h
to XXAAAh
Write XX90h
to XXAAAh
Write XXA0h
to XXAAAh
Write XX80h
to XXAAAh
Write XX80h
to XXAAAh
Write XX20h
to XXAAAh
Cycle 3
Read
identifier at
addr
XXX02h
Read value
at addr
XXX04h
Write word
to even
address
Write
XXAAh to
XXAAAh
Write
XXAAh to
XXAAAh
Cycle 4
Write
XX55h to
XX554h
Write
XX55h to
XX554h
Cycle 5
Write
XX10h to
XXAAAh
Write
XX30h to
new Sector
Cycle 6
DSM2150F5V
Write
XX30h to
new Sector
Cycle 7
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