DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 12

• Manufacturer Part Number: DSM2150F5V
• Description: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

DSM2150F5V
Runtime Control Registers
A block of 256 bytes is decoded inside the DSM
device for control and status registers. 50 registers
are used from the block of 256 locations to control
the output state of I/O pins, to READ I/O pins, to
control power management, to READ/WRITE
macrocells, and other functions at runtime. See
Table 4., page 13
dress of these 256 locations is referred to in this
data sheet as csiop (Chip Select I/O Port). Individ-
ual registers within this block are accessed with an
offset from the base address. Some DSPs can ac-
cess csiop registers using I/O memory with the
IOMS
bytes. When the DSM is configured for 16-bit op-
eration, csiop registers are read in byte pairs at
even addresses only. Care should be taken while
writing csiop registers to ensure the proper byte is
written within the byte pair. This is not a problem
for DSPs that support the BHE (Byte High Enable)
signal on the CNTL2 input pin, or WRL, WRH
(WRITE low byte, WRITE high byte) on the CNTL0
and PD3 input pins of the DSM2150F5V.
Memory Page Register
This 8-bit register can be loaded and read by the
DSP at runtime as one of the csiop registers. Its
outputs feed directly into both PLDs. The page
register can be used for special memory mapping
requirements and also for general logic.
I/O Ports
The DSM has 52 individually configurable I/O pins
distributed over the seven ports (Ports A, B, C, D,
E, F, and G). At least 32 I/O are available when
DSM2150F5V is connected with 8-bit data path,
and at least 24 I/O are available with 16-bit data
path. Each I/O pin can be individually configured
for different functions such as standard MCU I/O
ports or PLD I/O on a pin by pin basis. (MCU I/O
means that for each pin, its output state can be
controlled or its input value can be read by the
DSP at runtime using the csiop registers like an
MCU would do.)
The static configuration of all Port pins is defined
with the PSDsoft Express
tool. The dynamic action of the Ports pins is con-
trolled by DSP runtime software.
JTAG ISP Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port E. This serial in-
terface allows programming of the entire DSM de-
vice or subsections (that is, only Flash memory, for
example) without the participation of the DSP. A
blank DSM device soldered to a circuit board can
be completely programmed in 15 to 35 seconds.
12/73
strobe (if equipped). csiop registers are
for description. The base ad-
™
software development
The basic JTAG signals; TMS, TCK, TDI, and
TDO form the IEEE-1149.1 interface. The DSM
device does not implement the IEEE-1149.1
Boundary Scan functions. The DSM uses the
JTAG interface for ISP only. However, the DSM
device can reside in a standard JTAG chain with
other JTAG devices and it will remain in BYPASS
Mode while other devices perform Boundary
Scan.
ISP programming time can be reduced as much as
30% by using two more signals on Port E, TSTAT
and TERR in addition to TMS, TCK, TDI and TDO.
The FlashLINK
available from STMicroelectronics for $USD59
and PSDsoft Express software is available at no
charge from www.st.com/psm. That is all that is
needed to program a DSM device using the paral-
lel port on any PC or notebook. See
MING IN-CIRCUIT USING JTAG ISP, page
Power Management
The DSM has bits in csiop registers that are con-
figured at run-time by the DSP to reduce power
consumption of the CPLD. The Turbo Bit in the
PMMR0 register can be set to logic '1' and the
CPLD will go to Non-Turbo Mode, meaning it will
latch its outputs and go to sleep until the next tran-
sition on its inputs. There is a slight penalty in PLD
performance (longer propagation delay), but sig-
nificant power savings are realized.
Additionally, other bits in two csiop registers can
be set by the DSP to selectively block signals from
entering the CPLD which reduces power con-
sumption.
Both Flash memories automatically go to standby
current between accesses. No user action re-
quired.
Security and NVM Sector Protection
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copy-
ing. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memory and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again.
Additionally, the contents of each individual Flash
memory sector can be write protected (sector pro-
tection) by configuration with PSDsoft Express
This is typically used to protect DSP boot code
from being corrupted by inadvertent WRITEs to
Flash memory from the DSP.
™
JTAG programming cable is
PROGRAM-
49.
™
.