DSM2150F5V STMicroelectronics, DSM2150F5V Datasheet - Page 20

• Manufacturer Part Number: DSM2150F5V
• Description: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

DSM2150F5V
Reading Flash Memory
Under typical conditions, the DSP may read the
Flash memory using READ operations just as it
would a ROM or RAM device. Alternately, the DSP
may use READ operations to obtain status infor-
mation about a Program or Erase cycle that is cur-
rently in progress. Lastly, the DSP may use
instruction sequences to read special data from
these memory blocks. The following sections de-
scribe these READ instruction sequences.
Read Memory Contents
Flash memory is placed in the Read Array Mode
after Power-up, chip reset, or a Reset Flash mem-
ory instruction sequence (see
Table 6., page
contents of the Flash memory by using READ op-
erations any time the READ operation is not part
of an instruction sequence. Bytes are read from
even or odd addresses when the DSM2150F5V is
configured for 8-bit operation. Only 16-bit words
are read from even addresses when the
DSM2150F5V is configured for 16-bit operations.
Read Main Flash Identifier
The Main Flash memory identifier is read with an
instruction sequence composed of 4 operations: 3
specific WRITE operations and a READ operation
(see
ing the READ operation the appropriate internal
Sector Select (FS0-FS7) must be active. The iden-
tifier is E8h (or XXE8h for 16-bit mode). Not appli-
cable to Secondary Flash.
Read Memory Sector Protection Status
The Flash memory Sector Protection Status is
read with an instruction sequence composed of 4
operations: 3 specific WRITE operations and a
READ operation (see
6., page
01h (XX01h for 16-bit mode) if the Flash sector is
protected or 00h (XX00h or 16-bit mode) if the sec-
tor is not protected. Internal Sector Select (FS0-
FS7 or CSBOOT0-CSBOOT3) designates the
Flash memory sector whose protection has to be
verified.
Alternatively, the sector protection status can also
be read by the DSP accessing the Flash memory
Protection registers in csiop space. See the sec-
tion entitled “Flash Memory Sector Protect” for
register definitions.
20/73
Table 5., page 15
17). The READ operation will produce
17). The DSP can read the memory
Table 5., page 15
or
Table 6., page
Table 5., page 15
17). Dur-
or
Table
or
Reading the Erase/Program Status Bits
The device provides several status bits to be used
by the DSP to confirm the completion of an Erase
or Program cycle of Flash memory. These status
bits minimize the time that the DSP spends per-
forming these tasks and are defined in
7., page
times as needed. DQ8 - DQ15 are insignificant
and can be ignored when the DSM2150F5V is
configured to operate in 16-bit mode, however, the
READ operation must occur on an even address
boundary.
For Flash memory, the DSP can perform a READ
operation to obtain these status bits while an
Erase or Program instruction sequence is being
executed by the embedded algorithm. See
GRAMMING FLASH MEMORY, page
tails.
Data Polling Flag (DQ7)
When erasing or programming in Flash memory,
the Data Polling Flag Bit (DQ7) outputs the com-
plement of the bit being entered for programming/
writing on the Data Polling Flag Bit (DQ7). Once
the Program instruction sequence or the WRITE
operation is completed, the true logic value is read
on the Data Polling Flag Bit (DQ7).
–
–
–
–
Data Polling is effective after the fourth WRITE
pulse (for a Program instruction sequence) or
after the sixth WRITE pulse (for an Erase
instruction sequence). It must be performed at
the address being programmed or at an
address within the Flash memory sector being
erased.
During an Erase cycle, the Data Polling Flag
Bit (DQ7) outputs a ’0.’ After completion of the
cycle, the Data Polling Flag Bit (DQ7) outputs
the last bit programmed (it is a ’1’ after
erasing).
If the byte/word to be programmed is in a
protected Flash memory sector, the
instruction sequence is ignored.
If all the Flash memory sectors to be erased
are protected, the Data Polling Flag Bit (DQ7)
is reset to ’0’ for t
the previous addressed byte. No erasure is
performed.
19. The status bits can be read as many
TIMOUT
, and then returns to
22, for de-
Table
PRO-