XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 109

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

12.1.11 Read-Modify-Write Instructions
12.1.12 Jump/Branch Instructions
MC68HC05JB3
REV 1
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register. The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is
met. If the test condition is not met, the branch is not performed. All branch
instructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of any
readable bit in the first 256 memory locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of
the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU finds the conditional branch destination by adding the
Arithmetic Shift Left
Arithmetic Shift Right
Clear Bit in Memory
Set Bit in Memory
Clear
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left
Logical Shift Right
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
Table 12-2. Read-Modify-Write Instructions
INSTRUCTION SET
Instruction
November 5, 1998
GENERAL RELEASE SPECIFICATION
Mnemonic
BCLR
BSET
COM
NEG
ROR
ASR
DEC
ROL
CLR
LSR
ASL
LSL
TST
INC
MOTOROLA
12-5