XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 63

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC05JB3
REV 1
When the input capture circuitry detects an active edge on the TCAP pin, it
latches the contents of the free-running timer counter registers into the input cap-
ture registers as shown in Figure 9-6.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter val-
ues at successive edges of opposite polarity measures the pulse width of the sig-
nal.
The input capture registers are made up of two 8-bit read-only registers (ICRH,
ICRL) as shown in Figure 9-9. The input capture edge detector contains a Schmitt
trigger to improve noise immunity. The edge that triggers the counter transfer is
defined by the input edge bit (IEDG) in the TCR. Reset does not affect the con-
tents of the input capture registers.
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
ICRH
$0014
ICRL
$0015
U = UNAFFECTED BY RESET
reset:
reset:
W
W
R
R
V
DD
ICRH7
ICRL7
BIT 7
V
Figure 9-8. TCAP Input Comparator Output
U
U
÷ 2
Figure 9-9. Input Capture Registers (ICRH, ICRL)
DD
ICRH6
ICRL6
BIT 6
U
U
November 5, 1998
ICRH5
ICRL5
BIT 5
16-BIT TIMER
U
U
Output of Comparator
ICRH4
ICRL4
BIT 4
Time
U
U
Signal on TCAP pin
ICRH3
GENERAL RELEASE SPECIFICATION
ICRL3
BIT 3
U
U
ICRH2
ICRL2
BIT 2
U
U
ICRH1
ICRL1
BIT 1
U
U
MOTOROLA
ICRH0
ICRL0
BIT 0
U
U
9-7