XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 93

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

10.5.7 USB Status Register (USR)
MC68HC05JB3
REV 1
ENABLE2 — Endpoint 2 Enable
ENABLE1 — Endpoint 1 Enable
STALL2 — Endpoint 2 Force Stall Bit
STALL1 — Endpoint 1 Force Stall Bit
RSEQ — Endpoint 0 Receive Sequence Bit
SETUP — SETUP Token Detect Bit
USR
$003D
This read/write bit enables Endpoint 2 and allows the USB to respond to IN
packets addressed to Endpoint 2. Reset clears this bit.
This read/write bit enables Endpoint 1 and allows the USB to respond to IN
packets addressed to Endpoint 1. Reset clears this bit.
This read/write bit causes Endpoint 2 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. Reset clears
this bit.
This read/write bit causes Endpoint 1 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. Reset clears
this bit.
This read only bit indicates the type of data packet last received for Endpoint 0
(DATA0 or DATA1).
This read only bit indicates that a valid SETUP token has been received.
reset:
1 = Endpoint 2 is enabled and can respond to an IN token.
0 = Endpoint 2 is disabled.
1 = Endpoint 1 is enabled and can respond to an IN token.
0 = Endpoint 1 is disabled.
1 = Send STALL handshake.
0 = Default.
1 = Send STALL handshake.
0 = Default.
1 = DATA1 Token received in last Endpoint 0 receive.
0 = DATA0 Token received in last Endpoint 0 receive.
1 = Last token received for Endpoint 0 was a SETUP token.
0 = Last token received for Endpoint 0 was not a SETUP token.
W
R
RSEQ
BIT 7
U
Figure 10-26. USB Status Register (USR)
= Unimplemented
SETUP
UNIVERSAL SERIAL BUS MODULE
BIT 6
U
November 5, 1998
BIT 5
U
0
BIT 4
U
0
RPSIZ3
GENERAL RELEASE SPECIFICATION
BIT 3
U
RPSIZ2
BIT 2
U
RPSIZ1
BIT 1
U
MOTOROLA
RPSIZ0
BIT 0
U
10-25