AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 110

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

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110
SERR
RMABORT Received Master Abort. RM-
RTABORT Received
• In master mode, during the data
phase of all memory read com-
mands.
In master mode, during the data
phase of the memory write com-
mand, the Am79C971 controller
sets the PERR bit if the target re-
ports a data parity error by as-
serting the PERR signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
PERR is set by the Am79C971
controller and cleared by writing a
1. Writing a 0 has no effect.
PERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
when the Am79C971 controller
detects an address parity error
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
SERR is set by the Am79C971
controller and cleared by writing a
1. Writing a 0 has no effect.
SERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
ABORT
Am79C971 controller terminates
a master cycle with a master
abort sequence.
RMABORT
Am79C971
cleared by writing a 1. Writing a 0
has no effect. RMABORT is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
ABORT is set when a target ter-
minates an Am79C971 master
cycle with a target abort se-
quence.
RTABORT
Am79C971
Signaled SERR. SERR is set
is
Target
is
is
set
controller
controller
set
set
Abort.
when
by
by
and
RT-
and
the
the
the
Am79C971
11
10-9
8
7
DATAPERR
STABORT
DEVSEL
FBTBC
cleared by writing a 1. Writing a 0
has no effect. RTABORT is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
STABORT is read only.
DEVSEL is read only.
During the data phase of all
memory read commands, the
Am79C971 controller checks for
parity error by sampling the
AD[31:0] and C/BE[3:0] and the
PAR lines. During the data phase
of all memory write commands,
the Am79C971 controller checks
the PERR input to detect whether
the target has reported a parity
error.
DATAPERR
Am79C971
cleared by writing a 1. Writing a 0
has no effect. DATAPERR is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
ro; write operations have no ef-
fect. The Am79C971 controller
will never terminate a slave ac-
cess with a target abort se-
quence.
is set to 01b (medium), which
means that the Am79C971 con-
troller will assert DEVSEL two
clock periods after FRAME is as-
serted.
Data
DATAPERR is set when the
Am79C971 controller is the cur-
rent bus master and it detects a
data parity error and the Parity
Error Response enable bit (PCI
Command register, bit 6) is set.
Read as one; write operations
have no effect. The Am79C971
controller is capable of accepting
fast back-to-back transactions
with the first transaction address-
ing a different target.
Send Target Abort. Read as ze-
Device Select Timing. DEVSEL
Fast
Back-To-Back
Parity
is
controller
Error
set
Detected.
Capable.
by
and
the