AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 256

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

16)
17)
AM79C971A SYSTEM DESIGN HINTS
1) In 100 Mb/s mode, if the device reports excessive Transmit Underflows, set the NOUFLO bit (BCR18, bit 11) to
2) In a system which does not use the reset pulse (RST#) for a warm boot reset (also known as Ctrl-Alt-Del reset),
3) In the 100Mb/s Full Duplex mode, the expansion bus clock (which is typically connected to the PCI bus clock)
4) When in auto-polling mode and no receive descriptors are available, the transmitter will not transmit until either a
F-4
Workaround: Do not allow a chain of TX descriptors to include a descriptor which previously was an end of
chain (EOP) and which is the last TX EOP descriptor for which the status has been returned. Here is a sug-
gested method for the workaround:
Status: No current plan to fix this erratum.
Symptom: Collision LED does not show the collision status of the MII bus.
Implication: Very minor, collision LED will not show the status.
Workaround: None.
Status: No current plan to fix this erratum.
Symptom: During the automatic read of the EEPROM, such as after hardware reset or when the PREAD bit
is set in the BCR19, the device drives the EECS and EESK signal pins simultaneously. The EECS is driven
high at the same time when the EESK is driving low. This violates the EEPROM clock low to chip select setup
time (tSKS) parameter, which should be 100ns.
Implication: None. Even though the tSKS parameter is technically violated, the relationship between EESK
(clock), EECS (chip select), and EEDI (data in) signals is such that the device will not detect a false opcode.
This is how these signals relate to each other. EESK starts toggling from a high level. It clocks twice before
the EECS is asserted and continues toggling. The EEDI input is driven low at the same time that the EESK
starts toggling and stay low for four clocks after the assertion of the EECS. Since the EEDI is low when the
EECS is asserted, no false opcode is detected by the EEPROM.
Workaround: None needed. An external circuit may be used to delay the EECS signal by 100ns from the fall-
ing edge of the EESK signal
Status: No current plan to fix this erratum.
1. BCR18 contents are programmable either through the EEPROM or software driver.
the PCI-SIG recommends that the BIOS should disable bus mastering capability of the PCI bus mastering de-
vices early in the reboot cycle. The disabling of the bus mastering capability can be accomplished by resetting
the BMEN bit in the PCI Command Register (bit 2, Offset 04h) of the device’s PCI configuration space. This
recommendation should be followed to avoid possible system hang.
speed needs to be at 33MHz. Any slower speed may cause under/over flow condition.
receive descriptor is available or the transmit demand bit (TDMD, CSR0, bit 3) is set. If there are no receive
descriptors available, only one packet will be transmitted for every TDMD.
The device driver’s TX Write pointer (TX_W) points to first TX descriptor with OWN = 0
The device driver’s TX Read pointer (TX_R) points to the last TX descriptor with OWN=0
As the TX_R pointer is advancing in the chain, if the EOP bit is set then set a device driver TX_Last
Then when a new frame is to be transmitted:
EOP pointer (TX_L) = Current TX_R pointer
1) If a single descriptor is needed
2) If buffer chaining
if TX_R >TX_W, then a descriptor is available
if TX_L =TX_W, then TX_R -TX_W descriptors are available
else only TX_L - TX_W descriptors are available