AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 164

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

4-0
BCR17: I/O Base Address Upper
Bit
31-16 RES
15-0
BCR18: Burst and Bus Control Register
Note: Note that bits 15-0 in this register are program-
mable through the EEPROM.
Bit
31-16 RES
15-12 ROMTMG
164
AUIFD (bit
1)
X
0
1
RES
IOBASEU
Name
Name
FDEN
0)
0
1
1
Reserved locations. Written as
zeros, read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Reserved
H_RESET, the value in this regis-
ter will be undefined. The settings
of this register will have no effect
on any Am79C971 controller
function. It is only included for
software compatibility with other
PCnet family devices.
Reserved locations. Written as
zeros and read as undefined.
Expansion ROM Timing. The val-
ue of ROMTMG is used to tune
the
(BCR30) accesses to SRAM/
Flash/EPROM as well as all Ex-
pansion ROM accesses to Flash/
EPROM.
Read/Write accessible always.
IOBASEU is not affected by
S_RESET or STOP.
ROMTMG, during read opera-
tions, defines the time from when
the Am79C971 controller drives
the lower 8 or 16 bits of the Ex-
pansion Bus Address bus to
when the Am79C971 controller
latches in the data on the 8 or 16
bits of the Expansion Bus Data
inputs. ROMTMG, during write
operations, defines the time from
when the Am79C971 controller
drives the lower 8 or 16 bits of the
Expansion Bus Data to when the
Description
Description
(bit
timing
Effect on the AUI
Half-Duplex
Half-Duplex
Full-Duplex
Port
locations.
for
Table 32. Network Port Configuration
all
P R E L I M I N A R Y
EBDATA
10BASE-T Port
Effect on the
Half-Duplex
Full-Duplex
Full-Duplex
After
Am79C971
ROMTMG (bits 15-12)
Effect on the GPSI
Table 33. ROMTNG Programming Values
1h<=n <=Fh
Half-Duplex
Full-Duplex
Full-Duplex
Port
EBWE and EROMCS deassert.
The differences in the sizes of the
Expansion Bus Address and
Data busses is due to the differ-
ence in the access for SRAM ver-
sus Flash/EPROM.
The register value specifies the
time in number of clock cycles +1
according to Table 33.
Note: Programming ROMTNG
with a value of 0 is not permitted.
The access time for the Expan-
sion
(BCR30) device (t
read operations can be calculat-
ed by subtracting the clock to out-
put delay for the EBUA_EBA[7:0]
outputs (t
ing the input to clock setup time
for the EBD[7:0] inputs (t
from the time defined by ROMT-
MG:
t
*CLK_FAC - (t
The access time for the Expan-
sion ROM or for the EDBATA
(BCR30) device (t
write operations can be calculat-
ed by subtracting the clock to out-
put delay for the EBUA EBA[7:0]
outputs (t
the input to clock setup time for
SRAM/Flash/EPRO inputs (t
from the time defined by ROMT-
MG:
t
CLK_FAC - (t
ACC
ACC
Effect On the MII Port (ASEL =
No. of Expansion Bus Cycles
= ROMTMG * CLK period *
= ROMTMG * CLK period
ROM or
0, PORTSEL = MII)
v_A_D
v_A_D
Half-Duplex
Full-Duplex
Full-Duplex
v_A_D
v_A_D
n+1
) and by subtract-
) and by adding
the
) - (t
ACC
ACC)
) - (t
s_D
EDBATA
) during
s_D
during
)
)
s_D
s_D
)
)