AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 28

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

When RST is active, MIIRXFRTGE is an input for
NAND tree testing.
IEEE 1149.1 (1990) Test Access Port
Interface
TCK
Test Clock
TCK is the clock input for the boundary scan test mode
operation. It can operate at a frequency of up to 10
MHz. TCK has an internal pull up resistor.
TDI
Test Data In
TDI is the test data input path to the Am79C971 con-
troller. The pin has an internal pull up resistor.
TDO
Test Data Out
TDO is the test data output path from the Am79C971
controller. The pin is tri-stated when the JTAG port is in-
active.
TMS
Test Mode Select
A serial input bit stream on the TMS pin is used to de-
fine the specific boundary scan test to be executed.
The pin has an internal pull up resistor.
Power Supply Pins
AVDDB
Analog Power (3 Pins)
There are three analog +5 V supply pins that provide
power for the Twisted Pair and AUI drivers. Hence, they
are very noisy. Special attention should be paid to the
printed circuit board layout to avoid excessive noise on
these lines. Refer to Appendix B, Recommendation for
Power and Ground Decoupling, for details.
AVSSB
Analog Ground (1 Pins)
There is one analog ground pin that provides ground
for the Twisted Pair and AUI drivers. Hence, it is very
noisy. Special attention should be paid to the printed
circuit board layout to avoid excessive noise on these
lines. Refer to Appendix B, Recommendation for Power
and Ground Decoupling, for details.
28
Output
Power
Power
Input
Input
Input
Am79C971
VDD_PLL
PLL Power (1 Pin)
There is one analog PLL +5 V supply pin. Special at-
tention should be paid to the printed circuit board layout
to avoid excessive noise on this line. Refer to Appendix
B, Recommendation for Power and Ground Decou-
pling, for details.
VSS_PLL
PLL Ground (1 Pin)
There is one analog PLL ground pin. Special attention
should be paid to the printed circuit board layout to
avoid excessive noise on this line. Refer to Appendix B,
Recommendation for Power and Ground Decoupling,
for details.
VDDB
I/O Buffer Power (5 Pins)
There are five power supply pins that are used by the
input/output buffer drivers. All VDDB pins must be con-
nected to a +5 V supply.
VSSB
I/O Buffer Ground (13 Pins)
There are thirteen ground pins that are used by the PCI
bus input/output buffer drivers.
VDD_PCI
PCI I/O Buffer Power (5 Pins)
There are five power supply pins that are used by the
PCI input/output buffer drivers. In a system with +5 V
signaling environment, all VDD_PCI pins must be con-
nected to a +5 V supply. In a system with +3.3 V signal-
ing environment, all VDD_PCI pins must be connected
to a +3.3 V supply.
VDD
Digital Power (4 Pins)
There are four power supply pins that are used by the
internal digital circuitry. All VDD pins must be con-
nected to a +5 V supply.
VSS
Digital Ground (6 Pins)
There are six ground pins that are used by the internal
digital circuitry.
Power
Power
Power
Power
Power
Power
Power