AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 34

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

During the boot procedure, the system will try to find an
Expansion ROM. A PCI system assumes that an Ex-
pansion ROM is present when it reads the ROM signa-
ture 55H (byte 0) and AAH (byte 1). A design without
Expansion ROM can guarantee that the Expansion
ROM detection fails by connecting two adjacent EBD
pins together.
Slave Cycle Termination
There are three scenarios besides normal completion
of a transaction where the Am79C971controller is the
target of a slave cycle and it will terminate the access.
Disconnect When Busy
The Am79C971controller cannot service any slave ac-
cess while it is reading the contents of the EEPROM.
Simultaneous access is not possible to avoid conflicts,
since the EEPROM is used to initialize some of the PCI
configuration space locations and most of the BCRs.
The EEPROM read operation will always happen auto-
matically after the deassertion of the RST pin. In addi-
tion, the host can start the read operation by setting the
PREAD bit (BCR19, bit 14). While the EEPROM read
is on-going, the Am79C971controller will disconnect
any slave access where it is the target by asserting
STOP together with DEVSEL, while driving TRDY high.
STOP will stay asserted until the end of the cycle.
Note that I/O and memory slave accesses will only be
disconnected if they are enabled by setting the IOEN or
MEMEN bit in the PCI Command register. Without the
enable bit set, the cycles will not be claimed at all.
Since H_RESET clears the IOEN and MEMEN bits for
the automatic EEPROM read after H_RESET, the dis-
connect only applies to configuration cycles.
A second situation where the Am79C971controller will
generate a PCI disconnect/retry cycle is when the host
tries to access any of the I/O resources right after hav-
ing read the Reset register. Since the access gener-
ates an internal reset pulse of about 1 s in length, all
further slave accesses will be deferred until the internal
reset operation is completed. See Figure 6.
Disconnect Of Burst Transfer
The Am79C971controller does not support burst ac-
cess to the configuration space, the I/O resources, or to
the Expansion Bus. The host indicates a burst transac-
tion by keeping FRAME asserted during the data
phase. When the Am79C971controller sees FRAME
and IRDY asserted in the clock cycle before it wants to
assert TRDY, it also asserts STOP at the same time.
The transfer of the first data phase is still successful,
since IRDY and TRDY are both asserted. See Figure 7.
34
Am79C971
Figure 7. Disconnect Of Slave Burst Transfer - No
Figure 6.
DEVSEL
FRAME
TRDY
STOP
IRDY
DEVSEL
C/BE
FRAME
PAR
CLK
TRDY
STOP
AD
IRDY
C/BE
CLK
PAR
AD
Disconnect Of Slave Cycle When Busy
1
1
Host Wait States
ADDR
CMD
ADDR
CMD
2
2
PAR
PAR
3
DATA
BE
3
DATA
BE
4
PAR
4
PAR
5
5
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