AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 119

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

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12
11
10
9
8
7
6
RES
MISSM
MERRM
RINTM
TINTM
IDONM
RES
DXSUFLO
written as zero.
set, the MISS bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
MISSM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
is set, the MERR bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
MERRM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
is set, the RINT bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
TINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
IDONM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
written as zeros.
flow error.
When DXSUFLO (CSR3, bit 6) is
set to 0, the transmitter is turned
Reserved location. Read and
Missed Frame Mask. If MISSM is
Memory Error Mask. If MERRM
Receive Interrupt Mask. If RINTM
Transmit
Initialization
Reserved location. Read and
Disable Transmit Stop on Under-
Interrupt
Done
Mask.
Mask.
Am79C971
If
If
5
LAPPEN
off when an UFLO error occurs
(CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C971 controller gracefully
recovers from an UFLO error. It
scans the transmit descriptor ring
until it finds the start of a new
frame and starts a new transmis-
sion.
Read/Write accessible always.
DXSUFLO
H_RESET or S_RESET and is
not affected by STOP.
Setting LAPPEN to a 1 also en-
ables the Am79C971 controller to
read the STP bit of receive de-
scriptors. The Am79C971 con-
troller
information to determine where it
should begin writing a receive
packet’s data. Note that while in
this mode, the Am79C971 con-
troller can write intermediate
packet data to buffers whose de-
scriptors do not contain STP bits
set to 1. Following the write to the
last descriptor used by a packet,
the Am79C971 controller will
scan through the next descriptor
entries to locate the next STP bit
that is set to a 1. The Am79C971
controller will begin writing the
next packets data to the buffer
pointed to by that descriptor.
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors that are allocated be-
tween descriptors that contain
Enable. When set to a 1, the
LAPPEN bit will
Am79C971 controller to generate
an interrupt following the descrip-
tor write operation to the first buff-
er of a receive frame. This
interrupt will be generated in ad-
dition to the interrupt that is gen-
erated following the descriptor
write operation to the last buffer
of a receive packet. The interrupt
will be signaled through the RINT
bit of CSR0.
Look Ahead Packet Processing
will
is
use
cleared
cause the
the
STP
119
by