SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 32

• Manufacturer Part Number: SH3100IMTR
• Description: Supervisory IC with I2C Interface and PWM
• Manufacturer: SEMTECH [Semtech Corporation]

© 2006 Semtech Corp.
POWER MANAGEMENT
Register Descriptions
Register Name FLLConfig
Address(hex): 22
SS Enable
Bit No.
Bit 7
[6:5]
[7]
[2]
[1]
[0]
Description
Spread Spectrum Enable
THIS REGISTER IS FUSE
INITIALIZED
Spread Spectrum Configuration
FineLock
CoarseLock
FLLEnable
Bit 6
SS Config
(continued)
Bit 5
Description
Bit Value
Bit 4
00
01
10
11
0
1
0
1
0
1
0
1
32
(R/W) Sets up the Frequency
Locked Loop (FLL)
Value Description
Spectrum Spreading is disabled
Spectrum Spreading is enabled
Note that this register may not be changed if the
App-specificFuseWP bit in the WriteProtects register is set
Spreading bandwidth = 16 kHz
Spreading bandwidth = 32 kHz
Spreading bandwidth = 64 kHz
Spreading bandwidth = 128 kHz
Note that this register may not be changed if the
App-specificFuseWP bit in the WriteProtects register is set
If the FLL is enabled locked, then it remains locked and tracks
the 32.768 kHz clock
Least significant bank of the HFDCO is adjusted with a
successive approximation algorithm to achieve a fast (4ms) lock
with only minor frequency excursions. This is mainly used to
return CLK0/1 to optimum accuracy following a long sleep
(HFDCO off) during which the temperature may have changed
substantially, which would lead to a slight error on the initial
startup frequency before the FLL drifted back to lock
If the FLL is enabled locked, then it remains locked and tracks
the 32.768 kHz clock
The FLL uses a successive approximation algorithm to rapidly
(30 ms) adjust the FLL to a new setting in the FLLDivideRatio
register. There may be substantial frequency excursions on
CLK0/CLK1 (if enabled for HF) while locking is taking place.
Once locked, the FLL continues to track the 32.768 kHz source
FLL is disabled. HFDCO free-runs with an accuracy of ± 0.5%
FLL is enabled – the HFDCO tracks the 32.768 kHz source
based on the FLLDivideRatio register.
FLLEnable is by default 0 until the crystal oscillator is stable,
and then it is automatically set. If no crystal is connected, the
FLL remains disabled. In either case, the FLLEnable bit can be
overridden by software
Bit 3
Fine Lock
Bit 2
Default Value: 0000 0000
Reset Event: P, W, B
Coarse Lock
Bit 1
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SH3100
Enable FLL
Bit 0