SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 48

• Manufacturer Part Number: SH3100IMTR
• Description: Supervisory IC with I2C Interface and PWM
• Manufacturer: SEMTECH [Semtech Corporation]

Initial Power-Up
When VDD is fi rst applied to the chip, the following
sequence of events occurs:
1. As VDD starts to rise, the internal references,
regulators, and oscillator start to power up. Once VDD
gets to approximately 0.9V, the internal power-on reset
is asserted and the NRST output pin is guaranteed
to be asserted Low. If an external 32.768kHz crystal
is connected, it also starts to power up. (The internal
oscillator is running long before the crystal oscillator.) The
VBAK regulator starts up if VBAK is present, however if
VBAK is applied before VDD, then it has no effect on chip
operation.
2. After a few hundred microseconds, the internal VREG
regulator supplying the core logic starts to power up. VREG
settles at approximately 1.6V. If VDD is ramping slowly,
then VREG tracks with VDD.
3. As VREG increases, the core logic starts to enter a
functional state and is held in its power on reset state.
Battery backup mode is inhibited to ensure the chip starts
up in VDD mode.
4. Once VREG is above 0.9V, internal power-on reset
is negated, and the chip waits for VDD to exceed the
minimum VBO threshold of 1.7V + Vhys. (Vhys = Rising
threshold hysteresis = 25mV to 100mV).
5. Once VDD passes the minimum VBO threshold, the
fuses are read, the calibration and confi guration settings
are applied (including the new VBO threshold), and the
SH3100 is placed into the appropriate operating mode.
If the mode allows the SNSE pin to determine the reset
duration, then the state of the SNSE pin is read and the
appropriate duration selected. If not, the reset duration
defaults to the fuse setting.
6. Depending on the mode selected, the chip behavior
then proceeds as one of the following:
© 2006 Semtech Corp.
POWER MANAGEMENT
Applications Information
48
Standard Operation. VDD Settles at Greater than the
Programmed VBO
1. The general-purpose DAC/comparator block and PWM
outputs are disabled.
2. Since VDD is greater than the VBO threshold, a counter
is started which times the following events.
3. Four ms after the new VBO Reset threshold is exceeded;
4. At the end of the VBO Reset duration period (as selected
5. The micro controller may now communicate with
6. Battery backup facility is enabled.
7. If an external crystal is connected, then the logic monitors
seconds of power-up, then the crystal oscillator circuitry
CLK0 starts at the fuse-programmed frequency. CLK1
also starts if fuse enabled.
by SNSE), NRST is negated.
the output from the crystal oscillator clock. Once 1024
cycles have been observed to indicate that it is running
in stable operation, then the logic switches over to run on
the crystal clock and shuts down the internal oscillator
to save power. The HFDCO is then switched from free-
running mode to FLL locking mode and smoothly pulls
into lock. This is done to avoid having to wait for the
crystal oscillator to start up before the SH3100 starts to
function. If the crystal oscillator does not start within 10
is disabled to save power.
the SH3100.
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