SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 67

• Manufacturer Part Number: SH3100IMTR
• Description: Supervisory IC with I2C Interface and PWM
• Manufacturer: SEMTECH [Semtech Corporation]

Auto-PWM Engine Features (Cont.)
•
Erratum
The Automatic Fan speed control requires correction as
follows:
•
•
This drastically reduces the utility of the automatic fan
control mode. However, since this mode implements au-
tomatic temperature measurement and SNSE pin moni-
toring, it may be useful to enable this mode and then have
the microcontroller read the temperature register regular-
ly and manually adjust the starting PWM setting accord-
ing to the temperature. Setting the increment register to
zero means the PWM rate stays set at the value loaded
into the starting PWM register. This reduces the time the
microcontroller needs for reading temperature and moni-
toring the SNSE pin in full manual mode.
© 2006 Semtech Corp.
POWER MANAGEMENT
Functional Descriptions
The main control registers are loaded on powerup
with values corresponding to a minimum temperature
of 40°C, minimum duty cycle of 25%, and a duty cycle
step size of 17, which gives a maximum temperature
of 85°C. The ForceDACValue register is set to 11 to
give a comparator reference level of 76mV, which
is the switching threshold for the SNSE input. All of
these registers can be overridden at any time by I
access.
With the power-up default settings, once the tempera-
ture rises above 40ºC, the SH3100 kick-starts the fan
at 100% for 1 second, and then starts incrementing
the PWM duty cycle (at 1.66%/ºC) from its starting po-
sition of 25% until it reaches its target duty cycle for
that temperature. This is correct.
As the temperature drops, the PWM duty cycle should
track down with temperature. What happens, how-
ever, is that the duty cycle drops immediately to 25%,
and stays at this rate until the temperature rises above
the maximum that it reached before it started drop-
ping. The duty cycle then starts to increment the duty
cycle as before until it reaches its target duty cycle
for the new temperature. This means that automatic
temperature regulation controlled by the fan would
not function correctly.
(continued)
2
C
67
Manual PWM Control
When the SMPSMode bits are set for NORMAL operation
(i.e. “00”), the PWM output can be manually set up to give
any duty cycle from 0 to 100% in approximately 0.1% steps
(1024 steps). The repeat rate is 1024 cycles of the CLK1
frequency. CLK1 output does not need to be enabled.
Thus for CLK1 at 32MHz, PWM repeat rate is 32μs, with
a minimum pulse width of 31.25ns, and if CLK1 is set to
244Hz, then the PWM repeat rate is over 4 seconds, with
a minimum pulse width of approximately 4 ms.
In Manual mode, absence of SNSE pulses can still be de-
tected as interrupts, and SNSE activity can also be detect-
ed by setting the general-purpose comparator to SNSE,
and enabling the general-purpose comparator interrupt,
or by polling the Status register.
In Manual mode, temperature can be measured by ini-
tiating an ADC conversion of temperature as normal, al-
though while the conversion is taking place, the SNSE pin
can not be monitored.
This does bias the SNSE pin at a DC level of 440 mV, and
negative transients on the small commutation sense resistor
(Rsense) are coupled through the fi lter and are detected as
commutation pulses on the SNSE input when they cross the
76mV threshold.
clude a simple high pass fi lter between the sense resistor of
the fan drive transistor and the SNSE input on the SH3100.
This is required to allow only the high speed commutation
pulses to pass through to the SNSE pin. If the fi lter is not pres-
ent, the switching pulses caused by the drive transistor could
be mistaken for commutation pulses, so the SH3100 would
not be able to detect a fan stall condition when the commuta-
tion pulses stop. The Mode 3 circuit diagram in the application
diagrams section shows this fi lter. Recommended fi lter com-
ponent values assuming the default SNSE threshold of 76mV
are:
Note: For correct SNSE pin monitoring, it is necessary to in-
R1
R2
C1 1
Rsense
39 KΩ
15 KΩ
0 nF
2 to 5Ω
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