SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 35

• Manufacturer Part Number: SH3100IMTR
• Description: Supervisory IC with I2C Interface and PWM
• Manufacturer: SEMTECH [Semtech Corporation]

© 2006 Semtech Corp.
POWER MANAGEMENT
Register Descriptions
Register Name Status
Xtal Osc Stable
Address(hex): 32
Bit No.
Bit 7
[7]
[6]
[5]
[4]
[3]
[1]
[0]
Description
Xtal Oscillator
Stable
Comparator
Output
Internal
32kHz
oscillator
stable
AutoClkDetect
mode
RTCInvalid
SNSE activity
FLL Locked
Comparator
output
Bit 6
(continued)
Description
Internal 32kHz
osc stable
Bit Value
Bit 5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(R/W) Various device status flags
Value Description
Either the crystal oscillator has not yet stabilized or the ForceInternal32kHzOn bit
in the Config register has been set
1024 cycles of the crystal oscillator have been counted, and the crystal is
therefore considered stable
The comparator reference input is lower than the DAC voltage
The comparator reference input is higher than the DAC voltage
This bit can be polled to determine whether SNSE, VBAK, VDD or temperature are
above or below a preset threshold, or it can be used with the ForceDACValue
register to implement alternative ADC algorithms
The internal 32.768 kHz oscillator has been stable and accurate since the last
write to this bit
The supply voltage to the internal 32.768 kHz oscillator has at some point
dropped below 1.65 V, resulting in some loss of frequency accuracy. Once the
crystal has stabilized, this oscillator is redundant; this oscillator is turned off, and
this flag is then set
Writing 1 to this bit clears it
No edges have been observed on the CLKIN pin. CLK0 continues to run until
software clears the CLK0Enable flag in the CLK0Config register
Activity has been observed on CLKIN, which is assumed to be connected to the
XOUT of the μC. CLK0 stops in the same state as CLKIN, 4 cycles after CLKIN
stops, and resumes as soon as CLKIN toggles
AutoClkDetect mode is one of the prime features of μBuddy, enabling very fast
clock startup and shutdown by detecting the microcontroller’s own sleep mode
The RTC clock has been accurate since this flag was last cleared, and the RTC
accuracy is therefore assured
At some time since this bit was last cleared by software, both VDD and VBAK have
been insufficient to sustain an accurate clock to the RTC, and the RTC value
therefore can not be trusted
Writing 1 to this bit clears it
No activity has been observed on the SNSE pin during the last 32768 periods of
CLK1, whether or not CLK1 is enabled
Activity has been observed on SNSE during the past 32768 periods of CLK1
The FLL has not stabilized at the desired frequency, and may still be hunting
The FLL has locked to frequency and is stable
Note that this bit is invalid once spectrum spreading is enabled
AutoClkDetect
mode
Bit 4
35
RTC invalid
Bit 3
Bit 2
Default Value: 0010 1000
Reset Event: P, W, B
SNSE activity
Bit 1
www.semtech.com
SH3100
FLL locked
Bit 0