HDSP-3400 Agilent(Hewlett-Packard), HDSP-3400 Datasheet - Page 26

• Manufacturer Part Number: HDSP-3400
• Description: 20 mm (0.8 inch) Seven Segment Displays
• Manufacturer: Agilent(Hewlett-Packard)

The table below illustrates a typical acquisition timing. For this example, the symbol rate is one
half of the clock rate. The code rate is set to 5/6, which requires 13 trial and errors before node
sync is achieved. The carrier search logic requires 10 dwells at different frequencies (500 symbols
per dwell) before demodulator lock is achieved.
Table 12: Example of Acquisition Timing
Carrier Search
Viterbi Node Sync
Byte Sync
Deinterleaver Flush
Reed Solomon
Total Timing
The total time required for acquisition could vary widely, depending upon the carrier search range
and the time required for Viterbi node sync. For this example, however, the Byte Sync time and
the time required to flush the deinterleaver dominates the total time. If a 60MHz clock were
employed, the total acquisition time would be 0.963 milliseconds for this example
26
48,201
Bit Times
16,000
19,584
1,632
8,333
2,652
Symbols
11,750
26,950
5,000
1,591
9,600
979
Clock Cycles
10,000
19,200
23,500
57,840
3,182
1,958