HDSP-3400 Agilent(Hewlett-Packard), HDSP-3400 Datasheet - Page 29

• Manufacturer Part Number: HDSP-3400
• Description: 20 mm (0.8 inch) Seven Segment Displays
• Manufacturer: Agilent(Hewlett-Packard)

3.7 Clock Generation PLL
An integrated VCO is locked to MxN times a reference frequency provided by a external clock.
This programmable PLL consists of a PLL analog core, a reference divider with a divider ratio M, a
feedback divider with a divider ratio N, and a divider which askes the duty cycle 1/2.
Reference divider and feedback divider are used to synthesize various frequencies from a reference
frequency,
Since PLL synchronizes the frequency and phase of two signals, F
The following two PLL modes are provided to control PLL.
(1) PLL Enable mode : The internal clock is connected to the generated clock of the PLL.
(2) PLL Disable mode : The PLL is bypassed and the external clock is directly connected to the
More information can be found on the part of the write register.
Internal clock is calculated as follows
ext_clk
f
f
int_clk
ext_clk
f
M
ext_clk.
=
=
Reference
Divider
M
f
N
1/M
int_clk
N
f
ext_clk
internal clock.
F
F
Ref
Fb
F
IGURE
20: C
PLL Analog Core
LOCK
Feedback
Divider
1/N
S
IGNAL
G
ENERATION
Ref
and F
1/2
Fb
,
enable
1
0
int_clk
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