ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 13

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

ADE3XXX
2
2.1
YUV Video
PC Analog
YUV, YUVCLK
V,H,CSYNC
DVI Link
RX0-2, RXC
INR, G, B
ADE3XXX Functional Description
Global Control Block
The global control block is responsible for:
The global control block runs on the XCLK clock domain which is required to be active for
programming. The clock domains of all other blocks are set in the Global Control Block. For I²C
access, the requested block must be driven with a valid clock above 10 MHz. Clock domains are
shown in
To program the SCLK frequency synthesizer to a desired frequency (fout, in MHz), the following
equations apply:
Selecting Clock Sources
Power Control
I²C Control
SCLK Frequency Synthesizer Control
Block-by-Block Synchronous Reset Generation
Microcontroller
Figure
SCL, SDA
Global
Line Lock
DVI Rx (Analog)
I2C
ADC Digital I/F
ADC (Analog)
DVI Decoder
YUV to RGB
PLL
HDCP
2.
domain
XCLK
f
f
OUT
OUT
PWM
f
OUT
< 8 x f
< 4 x f
data
data
data
< 2 x f
Frequency Range
Re-Time
Table 3: SCLK Frequency Ranges
XCLK
XCLK
Sync
Measure
DMUX
XCLK
SMUX
Sync
Measure
Figure 2: Clock Domains
Data
AND f
AND f
domain
INCLK
AND f
OUT
OUT
OUT
4 x f
2 x f
Freq.Synth.
Scaler
f
domain
XCLK
SCLK
SCLK
XCLK
XCLK
ADE3XXX
domain
Sequencer
DOTCLK
Output
TCON
SDIV
FM Freq.
0
1
2
Synth.
Flicker
Detect
Global Control Block
ORA, OGA, OBA
ORB, OGB, OBB
OCLK
ODE, OHS, OVS
TCON
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