ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 78

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

Pulse Width Modulation (PWM) Block
78/88
PWM_CTRL0
PWM_CTRL1
PWM_PERIOD_L
PWM_PERIOD_H
PWM_DUTY_L
PWM_DUTY_H
PWM_OVERLAP_L
PWM_OVERLAP_H
PWM_STEP_DELAY
PWM_CYCLES_PER_FRAME_L
PWM_CYCLES_PER_FRAME_H
Register Name
0x01A0
0x01A1
0x01A2
0x01A3
0x01A4
0x01A5
0x01A6
0x01A7
0x01A8
0x01AA
0x01A9
Addr
Table 30: PWM Registers
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:4]
[3:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
PWM status
0: unlocked
1: locked
0: lock to CYCLES_PER_FRAME from the
free run state machine
1: lock to CYCLES_PER_FRAME register
setting
PWM_A polarity
0: active low
1: active high
PWM_B polarity
0: active low
1: active high
0: normal operation
1: force PWM outputs to polarity settings
0: change period or duty cycle at the end of
the current cycle
1: smooth change, period or duty cycle
increment/decrement every
PWM_STEP_DELAY cycle
0: free run
1: lock to out_vsync
0: disable PWM output
1: enable PWM output
Lock 2
0x0 = max
0x3 = typical
0xF = min
Lock gain (power of 2)
0x0 = max
0x6 = typical
0xF = min
Period-2 in Free-running mode, in XCLKs
Duty cycle of PWM in XCLKs
Non-overlap of PWMs in XCLKs
In smooth change mode, the number of
cycles skipped before the period/duty
registers are incremented/decremented
The number of cycles per frame in frame
lock mode when not using the internally
generated cycles per frame from a previous
freerun mode
nd
order gain (power of 2)
Description
ADE3XXX