ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 30

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

Sync Retiming Block
30/88
2.8
SRTXK_CSYNC_INV
SRTXK_SOG_THR_L
SRTXK_SOG_THR_H
SRTXK_CSYNC_THR_L
SRTXK_CSYNC_THR_H
YUV_INT
Sync Retiming Block
The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into
the XCLK and INCLK domains.
For the XCLK domain, SRT has the following functionality:
Register Name
Register Name
Retimes all sync signals going to SMEAS into the XCLK domain.
Extracts vertical sync from composite sync signals (ahsync and acsync pins)
Divides clocks by 1024 for activity detection purposes.
Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source.
Generates a coast signal in the XCLK domain for the LLPLL.
Table 12: Sync Retiming Registers (Sheet 1 of 2)
0x01E0
0x01E1
0x01E2
0x01E3
0x01E4
Table 11: YUV Registers (Sheet 2 of 2)
0x0702
Addr
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
R/W
R/W
R/W
R/W
Mode
[2]
[1]
[0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:3]
[7:0]
[7:0]
Bits
[7:6]
[5]
[4:2]
[1]
[0]
Bits
0x0
0x0
0x0
0x0
0x080
0x080
Default
0x0
0x0
0x0
0x0
Default
Reserved
invert filtered vert sync signal
invert composite sync signal
invert SOG signal
SOG vert sync extractor threshold [7:0]
Reserved
SOG vert sync extractor threshold [11:8]
composite sync vertical sync extractor
threshold [7:0]
Reserved
composite sync vertical sync extractor
threshold [11:8]
Reserved
0: VIP 8b mode
1: VIP 16b mode (skip 1 clock after
every 6 valid data)
YUV data input format
0x2: YUV 16-bit
0x4: YUV 8-bit
0x6: RGB
all others: Reserved
0: C-Y
1: Y-C
0: Cr-Cb
1: Cb-Cr
Description
Description
ADE3XXX