ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 17

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

ADE3XXX
2.2
GLBL_CLK_SRC_SEL_3
GLBL_IK_SRST
GLBL_DK_SRST
FM Frequency Synthesizer
The FM frequency synthesizer creates a clock equivalent to up to eight times the crystal input clock,
using a digital frequency synthesizer. The modulation period and amplitude are directly controlled
by I2C registers. The I2C interface runs in the LLK_CTRL clock domain, which must be active for
access.
The output frequency (f
follows:
Register Name
f
OUT
= f
XCLK
x 2
27+NDIV
OUT
Table 4: Global Registers (Sheet 4 of 4)
0x0012
0x0020
0x0040
Addr.
) is related to the 32-bit PHASE_RATE and crystal frequency (f
/ PHASE_RATE
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits
[6:4]
[2:0]
[3]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
[7]
[7]
Default
0x4
0x4
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Reserved
YUV clock source
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: YUVCLK pin (normal)
0x3: CLKIN pin
0x4: crystal clock
0x5: 0
0x6 - 0x7: Reserved
Reserved
DVI detection clock source
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: DVI detect clock (normal)
0x3: CLKIN pin
0x4: crystal clock
0x5: 0
0x6 - 0x7: Reserved
HDCP block reset synchronous to INCLK
DFT block reset synchronous to INCLK
ADC block reset synchronous to INCLK
SCALER block reset synchronous to INCLK
YUV block reset synchronous to INCLK
DVI block reset synchronous to INCLK
DMEAS block reset synchronous to INCLK
SMUX block reset synchronous to INCLK
Reserved
PGEN block reset synchronous to DOTCLK
OMUX block reset synchronous to DOTCLK
APC block reset synchronous to DOTCLK
OSD block reset synchronous to DOTCLK
GAMMA block reset synchronous to
DOTCLK
OSQ block reset synchronous to DOTCLK
SCALE block reset synchronous to DOTCLK
FM Frequency Synthesizer
Description
XCLK
17/88
) as