ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 77

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

ADE3XXX
2.24
OMUX_ DLY_GB4
OMUX_ DLY_GB6
OMUX_ DLY_RB0
OMUX_ DLY_RB2
OMUX_ DLY_R_B4
OMUX_ DLY_R_B6
OMUX_ DLY_TCON_0
OMUX_ DLY_TCON_2
OMUX_ DLY_TCON_4
OMUX_ DLY_TCON_6
OMUX_ DLY_VS_ENAB
OMUX_ DLY_CLK_HS
OMUX_CTRL_3
OMUX_REFCOUNT
Pulse Width Modulation (PWM) Block
The PWM B block generates two signals to control backlight inverter switching power components
directly. It is derived from XCLK and powered up independently of the DOTCLK and INCLK
domains. Frequency, duty cycle, polarity and overlap/non-overlap are programmable. The output
frequency can “free-run” or lock to output vsync.
Register Name
Table 29: Output Mux Registers (Sheet 3 of 3)
0x0C3E
0x0C3D
0x0C3C
0x0C3B
0x0C3A
0x0C39
0x0C38
0x0C37
0x0C36
0x0C35
0x0C34
0x0C33
0x0C51
0x0C52
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Mode
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:3]
[2]
[1]
[0]
[7:6]
[5:0]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
Pulse Width Modulation (PWM) Block
Delay for OGB5
Delay for OGB4
Delay for OGB7
Delay for OGB6
Delay for ORB1
Delay for ORB0
Delay for ORB3
Delay for ORB2
Delay for ORB5
Delay for ORB4
Delay for ORB7
Delay for ORB6
Delay for TCON1
Delay for TCON0
Delay for TCON3
Delay for TCON2
Delay for TCON5
Delay for TCON4
Delay for TCON7
Delay for TCON6
Delay for VSYNC
Delay for ENAB
Delay for CLK
Delay for HSYNC
Reserved
PWM mux mode
PWM enable
TCON data invert enable, with computed
data invert pin.
Reserved
returns a value that indicates the ADE gate
speed -- a function of temp and voltage
higher = faster logic
Description
77/88