ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 14

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

Global Control Block
14/88
GLBL_NULL_ADDR
GLBL_CLK_SRC_SEL_0
where f
generated by this block is f
For lower power operation, set all clock sources to the “zero” setting and also set the analog power
disables. In this condition, only the crystal clock domain (XCLK) runs and blocks in INCLK or
DOTCLK domains are not accessible by I2C.
To detect a DVI plug event and wake from a low power state, program the DVI detection clock
source select to the DVI detect clock and enable the analog power control for the DVI detect clock.
All other clock sources are set to zero.
Register Name
MD = INT(f
PE = INT((2
XCLK
is the external crystal frequency in MHz (typically 27). The maximum SCLK frequency
XCLK
15
) x (MD + 1 - f
f
f
OUT
x (2
f
f
OUT
OUT
OUT
f
Table 3: SCLK Frequency Ranges (Continued)
OUT
< f
(6 + NDIV - SDIV)
< f
< f
< f
Table 4: Global Registers (Sheet 1 of 4)
0x0000
0x0001
< f
Addr.
XCLK
XTAL
Frequency Range
XCLK
XCLK
XCLK
XCLK
/16 AND f
/8 AND f
/2 AND f
/4 AND f
x 2
XCLK
AND f
(2+NDIV)
Mode
R/W
R/W
R/W
OUT
x (2
OUT
OUT
OUT
OUT
) / f
(6 + NDIV - SDIV)
OUT
.
f
f
XCLK
f
f
XCLK
f
XCLK
XCLK
XCLK
Bits
[6:4]
[3:0]
[7:0]
[7]
)
/2
/16
/4
/8
/32
Default
0xA
0x5
0x0
0x0
) / f
OUT
DOTCLK source
Chip Revision ID
Reserved
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: FM freq synth (normal)
0x3: INCLK
0x4: CLKIN pin
0x5: crystal clock
0x6: 0
0x7: Reserved
INCLK source
0x0: YUVCLK pin (YUV Input)
0x1: DVI_PLLCLK (DVI Input)
0x2: ADCclock red
0x3: ADCclock green
0x4: ADC clock blue
0x5: SCLK freq synth
0x6: DVI detect clock
0x7: LLK PLL (ADC Input)
0x8: CLKIN pin
0x9: FM freq synth
0xA: crystal clock
0xB: 0
0xC - 0xF: Reserved
))
SDIV
3
4
5
6
7
Description
ADE3XXX