ADE3000SXT STMicroelectronics, ADE3000SXT Datasheet - Page 20

• Manufacturer Part Number: ADE3000SXT
• Description: LCD Display Engines with Integrated DVI/ ADC and YUV Ports
• Manufacturer: STMicroelectronics

Line Lock PLL Block
20/88
LLK_PLL_CTRL
LLK_PLL_MFACTOR_L
LLK_PLL_MFACTOR_H
LLK_PLL_HPERIOD_L
LLK_PLL_HPERIOD_H
LLK_PLL_PHASE_RATE_INIT_0
LLK_PLL_PHASE_RATE_INIT_1
LLK_PLL_PHASE_RATE_INIT_2
LLK_PLL_PHASE_RATE_INIT_3
LLK_PLL_PHASE_RATE_INIT_WR
LLK_PLL_TC_AEF
LLK_PLL_TC_BEF
LLK_PLL_TC_ALF
LLK_PLL_TC_BLF
LLK_PLL_TC_AES
LLK_PLL_TC_BES
LLK_PLL_TC_ALS
Register Name
Table 7: Line Lock PLL Registers (Sheet 2 of 4)
0x0801
0x0802
0x0803
0x0804
0x0805
0x0806
0x0807
0x0808
0x0809
0x080A
0x080B
0x080C
0x080D
0x080E
0x080F
0x0810
0x0811
Addr
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[7:6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:1]
[0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:6]
[5:0]
[7:6]
[5:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:6]
[5:0]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0280
0x0040
0x0
0xA
0xA
0x20
0x20
0x6
0x6
0x20
Default
Reserved
0: normal
1: diagnostic mode -- PLL uses only fine
error
0: normal
1: diagnostic -- coarse error is multiplied by
2
input hsync edge selection
0: rising edge
1: falling edge
sync on green input selection
0: composite sync (HSYNC pin)
1: sync on green (CSYNC pin)
0: normal
1: divide PLL clock by 2
0: normal
1: Free-running mode
f
When written to 1, the PLL phase rate is
initialized with the initial phase rate register.
Self clearing.
Reserved
Fast Time Constant A Exponent
Reserved
Fast Time Constant B Exponent
Fast Time Constant A Linear
Fast Time Constant B Linear
Reserved
Slow Time Constant A Exponent
Reserved
Slow Time Constant B Exponent
Slow Time Constant A Linear
number of clocks in a line
pulse width of synthetic hsync
Initial Phase Rate
Reserved
Reserved
Reserved
Reserved
OUT
= f
XTAL
x 2
Description
27+NDIV
/ PHASE_RATE
ADE3XXX