ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 100

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ZL50019

Manufacturer Part Number
ZL50019
Description
Enhanced 2 K Digital Switch with Stratum 4E DPLL
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet

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† Characteristics are over recommended operating conditions unless otherwise stated.
* Test condition is R
the time taken to discharge C
AC Electrical Characteristics
1
2
3
4
STio Delay - Active to High-Z
STio Delay - High-Z to Active
Output Drive Enable (ODE) Delay
- High-Z to Active
Output Drive Enable (ODE) Delay
- Active to High-Z
ODE
STio
CKi @ 4.096 MHz
CKi @ 8.192 MHz
CKi @ 16.384 MHz
CKi @ 4.096 MHz
CKi @ 8.192 MHz
CKi @ 16.384 MHz
Characteristic
L
= 1 k, C
t
ZD_ODE
HiZ
L
L
.
= 30 pF; high impedance is measured by pulling to the appropriate rail with R
- ST-BUS/GCI-Bus Output Tristate Timing
CKo0
FPo0
STio
STio
Figure 37 - Serial Output and External Control
Figure 38 - Output Drive Enable (ODE)
Valid Data
t
t
ZD_ODE
DZ_ODE
Sym.
Zarlink Semiconductor Inc.
t
t
DZ
ZD
Valid Data
ZL50019
Tristate
t
DZ_ODE
100
Min.
-2
-3
-8
-2
-3
-8
t
t
DZ
ZD
V
Typ.
CT
Valid Data
Tristate
V
HiZ
CT
Max.
260
138
260
138
77
77
77
77
8
7
0
8
7
0
V
V
CT
CT
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
, with timing corrected to cancel
Master Mode
Multiplied Slave Mode
Divided Slave Mode
Master Mode
Multiplied Slave Mode
Divided Slave Mode
Master or
Multiplied Slave Mode
Divided Slave Mode
Master or
Multiplied Slave Mode
Divided Slave Mode
Test Conditions
Data Sheet
V
V
CT
CT
*

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