ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 90

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

† Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics
Note 1:
Note 2:
10 Acknowledgement delay time.
12 RDY drive low to HiZ
11 Acknowledgement hold time.
1
2
3
4
5
6
7
8
9
CS
RD
WR
A0-A13
D0-D15
RDY
CS de-asserted time
RD setup to CS falling
WR setup to CS falling
Address setup to CS falling
RD hold after CS rising
WR hold after CS rising
Address hold after CS rising
Data setup to RDY high
Data hold after CS rising
From CS low to RDY high:
From CS high to RDY low
Registers
Memory
discharge C
A delay of 500 µs to 2 ms (see Section 18.2 on page 42) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
High impedance is measured by pulling to the appropriate rail with R
Characteristics
L
.
Figure 26 - Intel Non-Multiplexed Bus Timing - Read Access
†
- Intel Non-Multiplexed Bus Mode - Read Access
t
CSD
Sym.
t
t
t
t
t
t
Zarlink Semiconductor Inc.
CSD
t
t
t
t
t
t
AKD
AKH
AKZ
WS
WH
RH
DH
RS
AS
AH
DS
t
t
t
RS
AS
WS
ZL50019
Min.
15
10
10
90
5
0
0
0
8
7
4
Typ.
VALID ADDRESS
t
AKD
L
, with timing corrected to cancel time taken to
t
DS
Max.
185
VALID READ DATA
75
12
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
AH
AKH
t
DH
C
C
(Note 1)
C
C
C
(Note 1)
t
t
RH
WH
L
L
L
L
L
Test Conditions
t
= 50 pF
= 50 pF, R
= 50 pF
= 50 pF
= 50 pF, R
AKZ
Data Sheet
V
V
V
V
V
V
CT
CT
CT
CT
L
L
CT
CT
= 1 K
= 1 K
2