ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 65

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15 - 9
6 - 4
3 - 2
External Read Only Address: 004C
Bit
15
0
8
7
14
0
RFR2 - 0
RES1 - 0
Unused
Name
SLM
LST
13
0
Table 36 - Reference Change Status Register (RCSR) Bits - Read Only
Reserved
In normal functional mode, these bits are zero.
Slew Rate Limiter Status Bit
If the device sets this bit to high, the DPLL phase difference between the input and output
clocks is changing at the slew rate limit defined in the Slew Rate Limit Register (SRLR).
Lock Status Bit
If the device sets this bit to high, while the LDTR and LDIR registers are programmed
properly, the DPLL output clocks are locked to the selected input reference.
If this bit is low, the DPLL output clocks are not yet locked to the selected input reference.
Reference Frequency Indicator Bits
These bits represent the frequency of the selected reference indicated by the reference
bits (RES1 - 0) in this register.
Reference Select Indicator Bits: These bits indicate which one of the four reference
inputs (REF0 - 3 pins) is being selected by the device.
12
0
H
11
0
RFR2
10
0
0
0
0
0
1
1
1
1
RES1
0
0
1
1
9
0
Zarlink Semiconductor Inc.
RFR1
0
0
1
1
0
0
1
1
ZL50019
SLM
8
RES0
0
1
0
1
65
RFR0
0
1
0
1
0
1
0
1
LST
7
Description
Input Reference in use
RFR2
Frequency of the Selected
6
REF 0
REF 1
REF 2
REF 3
RFR1
16.384 MHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
Reference
19.44MHz
5
Reserved
8 kHz
RFR0
4
RES1
3
RES0
2
DPM1
Data Sheet
1
DPM0
0