ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 36

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

internal to the device and are synchronized to CKi and FPi. All specified frequencies are available on CKo[0:3] in
Multiplied Slave mode.
By default, the DPLL is disabled if the device is in Slave mode. However, the DPLL can be activated by
programming the SLV_DPLLEN bit in the Control Register. When the DPLL is enabled, CKo4, CKo5 and FPo5 will
be generated from the DPLL, while the other clocks and frame pulses will be generated based on CKi/FPi. In this
case the DPLL will be fully functional, including its capability of reference monitoring.
Note that an external oscillator is required whenever the DPLL is used.
Table 7, “ZL50019 Operating Modes” on page 36 summarizes the different modes of operation available within the
ZL50019. Each Major mode (explained below) has an associated Minor mode that is determined by setting the
relevant Input Control pins and Control Register bits (Table 16, “Control Register (CR) Bits” on page 48) indicated in
the table.
12.1
When the device is in Master mode, the DPLL is phase-locked to the one of four DPLL reference signals, REF0 to
REF3, which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz signal. The on-chip DPLL also offers reference switching and monitoring, jitter attenuation, freerun and
holdover functions. In this mode, STio0 - 31 are driven by a clock generated by the DPLL, which also provides all
the output clocks (CKo0 - 5) and frame pulses (FPo0 - 3 and FPo_OFF0 - 2).
12.2
When the device is in Divided Slave mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same amount of jitter as the input clock (CKi), but the output data rate cannot exceed the input data
rate defined by CKi. For example, if CKi is 4.096 MHz, the output data rate cannot be higher than 2.048 Mbps, and
the generated output clock rates cannot exceed 4.096 MHz. If the DPLL is not enabled, an external oscillator is
optional in Divided Slave mode.
Legend:
X
Reference Lock
REF0-3 = Normal
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
* CKi must be phase aligned (edge synchronous) to CLo0-3.
Clock Source
Multiplied
Divided
Master
Major
Slave
Slave
Operating Mode
Don’t care or not applicable.
Device
Master Mode Performance
Divided Slave Mode Performance
Loopback
8/16 M
8/16 M
8/16 M
8/16 M
Minor
CKi
4 M
4 M
4 M
4 M
Refers to what signal the output pins are locked to:
Refers to which clock samples STi and which clock outputs STo; STi applies when STio is input; STo applies when STio is output.
OSC_EN MODE_4M
1
1
0
1
0
Control
[1:0]
00
00
00
00
00
11
11
11
11
Input Pins
2 0MHz 4/8/16 M
20 MHz
20 MHz
OSCi
X
X
Table 7 - ZL50019 Operating Modes
Signal
8/16 M
8/16 M
8/16 M
8/16 M
CKi
4 M
4 M
4 M
4 M
X
Zarlink Semiconductor Inc.
OPM
[1:0]
01
X0
X1
11
00
ZL50019
SLV_DPLLEN CKi_LP
CR Register
36
X
1
0
1
0
Bits
X
0
1
CKi MULT REF0-3
Freerun, Holdover
CKo0-3
Reference Lock
CKi
or REF0-3
Output Clock Pins
CKo4-5 CKo0-3 CKo4-5
REF0-3
X
X
Yes
Enabled
Yes
Yes
Yes
No
No
Data Sheet
Cko2
CKi*
CKi
STi
Clock Source
Data Pins
(CKi MULT)
CKo0-3
CKo0-3
(DPLL)
Cko2
(CKi)
STo