AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 46

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

available. EAR must have a pulse width of at least
200 ns.
Note that setting the PROM bit (MAC Configuration
Control) will cause all receive packets to be received,
General Purpose Serial Interface (GPSI)
The GPSI port provides the signals necessary to
present an interface consistent with the non encoded
data functions observed to/from a LAN controller such
as the Am7990 Local Area Network Controller for
Ethernet (LANCE). The actual GPSI pins are function-
ally identical to some of the pins from the DAI and the
EADI ports, the GPSI replicates this type of interface.
The GPSI allows use of an external Manchester
encoder/decoder, such as the Am7992B Serial Inter-
face Adapter (SIA). In addition, it allows the MACE
device to be used as a MAC sublayer engine in a
repeater based on the Am79C980 Integrated Multiport
Repeater (IMR). Simple connection to the IMR Expan-
sion Bus allows the MAC to view all packet data pass-
ing through a number of interconnected IMRs, allowing
statistics and network management information to
be collected.
The GPSI functional pins are duplicated as follows:
IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test
Access Port is provided for board level continuity test
and diagnostics. All digital input, output and input/out-
put and input/output pins are tested. Analog pins,
including the AUI differential driver (DO ) and receiv-
46
Function
Receive Data
Receive Clock
Receive Carrier Sense
Collision
Transmit Data
Transmit Clock
Transmit Enable
PROM
1
0
0
0
0
Pin Configuration for GPSI Function
X
0
0
1
1
M/R
X
H
H
Type
EAM/R
O
O
I
I
I
I
I
Internal/External Address Recognition Capabilities
LANCE
RENA
RCLK
CLSN
TENA
TCK
No timing requirements
No timing requirements
Low for 200 ns within 512-bits after SFD
No timing requirements
Low for 200 ns within 8-bits after DA field
Pin
RX
TX
SRDCLK
STDCLK
TXDAT+
RXCRS
RXDAT
MACE
CLSN
TXEN
Required Timing
Pin
Am79C940
regardless of the programming of M/R or the state of
the EAM/R input. The following table summarizes the
operation of the EADI features.
ers DI , CI ), and the crystal input (XTAL1/XTAL2)
pins, are not tested.
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the MACE
device. For additional details, consult the IEEE Stan-
dard Test Access Port and Boundary-Scan Architec-
ture document (IEEE Std 1149.1–1990).
The boundary scan test circuit requires four pins (TCK,
TMS, TDI and TDO ), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an
instruction register, a data register array and a power
on reset circuit. Internal pull-up resistors are provided
for the TCK, TDI and TMS pins.
The TAP engine is a 16 state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. An
independent power on reset circuit is provided to
ensure the FSM is in the TEST_LOGIC_RESET state
at power up.
In addition to the minimum IEEE 1149.1 instruction
requirements (EXTEST, SAMPLE and BYPASS), three
additional instructions (IDCODE, TRI_ST and SET_I/
O) are provided to further ease board level testing. All
unused instruction codes are reserved.
EXTEST External Test
IDCode
Sample
TRI_ST
SET_I/0
Bypass
ame
Inst
IEEE 1149.1 Supported Instruction Summary
ID Code Inspection
Sample Boundary
Force Tristate
Control
BoundaryTo I/0
Bypass Scan
Description
All Received Frames
All Received Frames
Physical/Logical/Broadcast Matches
Physical/Logical/Broadcast Matches
All Received Frames
Received Messages
Data Reg
Selected
Bypass
Bypass
Bypass
ID Reg
BSR
BSR
Normal 0001
Normal 0010
Normal 0011
Normal
Mode
Reg
Test
Test
Code
0000
0100
1111
Inst