AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 59

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Retry Count (XMTRC)
The Transmit Retry Count should be read only in
response to a hardware interrupt request (INTR
asserted) when XMTINT is set in the Interrupt Register,
or after XMTSV is set in the Poll Register.The register
should be read before the Transmit Frame Status
register. Reading the Transmit Frame Status with
XMTSV set will cause the XMTRC value to be reset.
This register is read only.
EXDEF
MORE
ONE
DEFER
LCAR
RTRY
RES
RES
re-asserted until the XMTFS has
been read. The MACE device
does not retry after a late
collision.
More. Indicates that more than
one retry was needed to transmit
the frame. ONE, MORE and
RTRY are mutually exclusive.
One. Indicates that exactly one
retry was needed to transmit the
frame. ONE, MORE and RTRY
are mutually exclusive.
Defer. Indicates that MACE
device had to defer transmission
of the frame. This condition
results if the channel is busy
when the MACE device is ready
to transmit.
Loss of Carrier. Indicates that
the carrier became false during
a
device does not retry upon Loss
of Carrier. LCAR will not be set
when the DAI port is selected,
when the 10BASE-T port is se-
lected and in the link pass state,
or during any internal loopback
mode. When the 10BASE-T port
is selected and in the link fail
state, LCAR will will be reported
for any transmission attempt.
Retry Error. Indicates that all
attempts to transmit the frame
were unsuccessful, and that fur-
ther attempts have been abort-
ed. If Disable Retry (DRTRY in
the Transmit Frame Control reg-
ister) is cleared, RTRY will be
set when a total of 16 unsuc-
cessful attempts were made to
transmit the frame. If DRTRY is
set, RTRY indicates that the first
and only attempt to transmit the
frame was unsuccessful. ONE,
MORE and RTRY are mutually
exclusive.
TDTREQ will be de-asserted,
and will not be re-asserted until
the XMTFS has been read.
transmission.
RES
If
(REG ADDR 4)
RTRY
XMTRC[3-0]
The
is
MACE
set,
Am79C940
Bit
Bit 3-0
Bit 6-4
Bit 3-0
Receive Frame Control (RCVFC) (REG ADDR 5)
Bit
Bit 7-4
Bit 3
RES
RES
EXDEF
RES
[3-0]
RES
LLRCV
Name
Name
RES
RES
Description
Excessive Defer. The EXDEF bit
will be set if a transmit frame
waited for an excessive period
for transmission. An excessive
defer time is defined in accor-
dance with the following (from
page 34, section 5.2.4.1 of IEEE
Std 802.3h-1990 Layer Manage-
ment):maxDeferTime = {2 x
(max frame size x 8)} bits where
maxFrameSize = 1518 bytes
(from page 68, section 4.4.2.1 of
ANSI/IEEE
So, the maxDeferTime = 24288
bits = 2
+2
Reserved. Read as zeroes.
Always write as zeroes.
XMTRCTransmit Retry Count.
the count of the number of retry
attempts made by the MACE
device to transmit the current
transmit packet. The value of the
counter will be zero if the first
transmission attempt was suc-
cessful, and a maximum of 15 if
all retry attempts were utilized.
RTRY will be set in Transmit
Frame Status if all 16 attempts
were unsuccessful.
Description
Reserved. Read as zeroes.
Always write as zeroes.
Low
programmable option to allow
access to the Receive FIFO
before the 64-byte threshold has
been reached. When set, data
can be read from the RCVFIFO
once a low threshold (12-bytes
after SFD plus synchronization)
has been exceeded, causing
RDTREQ
RDTREQ will remain asserted
as long as one read cycle can be
performed on the RCVFIFO
(identical to the burst mode).
Indication of a valid read cycle
from the RCVFIFO will return
DTV asserted. Reading the
RCVFIFO before data is avail-
able, or while waiting for addi-
Contains
LLRCV
7
+2
6
Latency
14
+2
M/R
+ 2
5
to
12
RES
Std
+ 2
be
Receive.
802.3-1990).
11
ASTRPRCV
+ 2
asserted.
10
+ 2
59
A
9