AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 51

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Minimum frame size (excluding preamble,
including FCS)
Preamble/SFD size
FCS size
To be classed as a minimum size frame at the receiver,
the transmitted frame must contain:
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS
(Disable Transmit FCS) when the EOF is asserted indi-
cating the last byte/word of data for the transmit frame
is being written to the FIFO. The action of writing the
last data byte/word of the transmit frame, latches the
current contents of the Transmit Frame Control regis-
ter, and therefore determines the programming of
DXMTFCS for the transmit frame. When DXMTFCS =
0 the transmitter will generate and append the FCS to
the transmitted frame. If the automatic padding feature
is invoked (APAD XMT in Transmit Frame Control), the
FCS will be appended regardless of the state of DXMT-
FCS. Note that the calculated FCS is transmitted most
significant bit first. The default value of DXMTFCS is 0
after hardware or software reset.
Transmit Status Information
Although multiple transmit frames can be queued in the
Transmit FIFO, the MACE device will not permit loss of
Transmit Frame Status information. The Transmit
Frame Status and Transmit Retry Count can only be
buffered internally for a maximum of two frames. The
MACE device will therefore not commence a third
transmit frame, until the status from the first frame is
read. Once the Transmit Retry Count and Transmit
Frame Status for the first transmit packet is read, the
MACE device will autonomously begin the next trans-
mit frame, provided that a transmit frame is pending,
the XMTSP threshold has been exceeded (or the
Preamble + (Min Frame Size + FCS) bits
1010....1010
Preamble
Bits
62
64 bytes
4 bytes
8 bytes
SYNCH
Bits
11
2
512 bits
32bits
64 bits
Ethernet Format Data Frame
Bytes
Dest
Addr
6
Am79C940
Bytes
Srce
Addr
6
At the point that FCS is to be appended, the transmitted
frame should contain:
A minimum length transmit frame from the MACE
device will therefore be 576 bits, after the FCS is
appended.
The Ethernet specification makes no use of the LLC
pad field, and assumes that minimum length messages
will be at least 64 bytes in length.
XMT FIFO is full), the network medium is free, and the
IPG time has elapsed.
Indication of valid Transmit Frame Status can be
obtained by servicing the hardware interrupt and test-
ing the XMTINT bit in the Interrupt Register, or by poll-
ing the XMTSV bit in the Poll register if a continuous
polling mechanism is required. If the Transmit Retry
Count data is required (for loading, diagnostic, or man-
agement information), XMTRC must be read prior to
XMTFS. Reading the XMTFS register when the
XMTSV bit is set will clear both the XMTRC and
XMTFS values.
Transmit Exception Conditions
Exception conditions for frame transmission fall into
two distinct categories; those which are the result of
normal network operation and those which occur due
to abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the MACE device are:
(a)
(b)
sion attempts.
(a) The MACE device will ensure that collisions which
occur within 512 bit times from the start of transmission
(including preamble) will be automatically retried with
no host intervention. The Transmit FIFO ensures this
by guaranteeing that data contained within the Trans-
Preamble + (Min Frame Size – FCS) bits
Deletion of packets due to excessive transmis-
Collisions within the slot time with automatic retry
64
Bytes
Type
2
+
46—1500
Data
Bytes
(512
16235D-8
Bytes
FCS
4
– 32) bits
51